JP3832576B2 - WIRING BOARD, SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, PANEL MODULE, AND ELECTRONIC DEVICE - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board, a semiconductor device, a manufacturing method thereof, a panel module, and an electronic device.
[0002]
BACKGROUND OF THE INVENTION
In COF (Chip On Film), which is known as a semiconductor chip mounting form, it is difficult to prevent the substrate from warping or distortion. In particular, it is known to form a mark on the substrate to know its direction, etc. However, the formation of the mark makes the pattern on the substrate asymmetrical, so that the warpage and distortion of the substrate can be suppressed. It was difficult.
[0003]
The present invention solves the conventional problems, and an object of the present invention is to recognize at least the direction of the substrate and to suppress warping and distortion of the substrate.
[0004]
[Means for Solving the Problems]
(1) A wiring board according to the present invention comprises: a board;
A wiring pattern formed on the substrate;
A pair of dummy patterns formed on the substrate;
Have
The external shape of the pair of dummy patterns is a shape that is line-symmetric with each other,
The surface shape inside the outer shape of one of the dummy patterns has a mark,
The inside of the outer shape of the other dummy pattern has a surface shape different from the surface shape having the mark.
[0005]
According to the present invention, since the dummy pattern is formed on the substrate, the portion of the substrate where the wiring pattern is not formed is reduced, and the warpage and distortion of the substrate can be suppressed. In addition, since the shape of the pair of dummy patterns is axisymmetric, asymmetric substrate warpage and distortion are unlikely to occur. Further, at least the direction of the substrate can be recognized by the mark. The mark exists inside the outer shape of one dummy pattern and does not exist inside the outer shape of the other dummy pattern. However, since the outer shapes of both dummy patterns are axisymmetric, the warp and distortion of the asymmetric substrate Is unlikely to occur.
[0006]
(2) In this wiring board,
The wiring pattern is composed of one or more groups of wirings;
The wirings of each group may be formed so that one end thereof is aligned.
[0007]
(3) In this wiring board,
Each of the dummy patterns may be formed in a region surrounded by the wiring pattern.
[0008]
(4) In this wiring board,
The dummy pattern may be formed of the same material as the wiring pattern.
[0009]
(5) In this wiring board,
The mark may be a through hole formed in the dummy pattern.
[0010]
(6) In this wiring board,
The mark may be a through hole formed in the dummy pattern and the substrate.
[0011]
(7) In this wiring board,
The mark may be a through hole formed in the resin layer on the dummy pattern.
[0012]
(8) In this wiring board,
The pair of dummy patterns as a pair of first dummy patterns, and the mark as a first mark,
A pair of second dummy patterns;
The outer shape of the pair of second dummy patterns is a shape that is symmetrical with respect to each other with respect to a line that is a reference for symmetry of the pair of first dummy patterns,
The surface shape inside the outer shape of one of the second dummy patterns has a second mark,
The inside of the outer shape of the other second dummy pattern may have a surface shape different from the surface shape having the second mark.
[0013]
(9) In this wiring board,
The first mark is formed on one side with the symmetrical reference line as a boundary,
The second mark may be formed on the other side with the line serving as the reference of symmetry as a boundary.
[0014]
(10) In this wiring board,
The first and second marks may be different in size or shape.
[0015]
(11) A semiconductor device according to the present invention includes a substrate,
A wiring pattern formed on the substrate;
A pair of dummy patterns formed on the substrate;
A semiconductor chip mounted on the substrate and electrically connected to the wiring pattern;
Have
The external shape of the pair of dummy patterns is a shape that is line-symmetric with each other,
The surface shape inside the outer shape of one of the dummy patterns has a mark,
The inside of the outer shape of the other dummy pattern has a surface shape different from the surface shape having the mark.
[0016]
According to the present invention, since the dummy pattern is formed on the substrate, the portion of the substrate where the wiring pattern is not formed is reduced, and the warpage and distortion of the substrate can be suppressed. In addition, since the shape of the pair of dummy patterns is axisymmetric, asymmetric substrate warpage and distortion are unlikely to occur. Further, at least the direction of the substrate can be recognized by the mark. The mark exists inside the outer shape of one dummy pattern and does not exist inside the outer shape of the other dummy pattern. However, since the outer shapes of both dummy patterns are axisymmetric, the warp and distortion of the asymmetric substrate Is unlikely to occur.
[0017]
(12) In this semiconductor device,
The dummy pattern may not be electrically connected to the semiconductor chip.
[0018]
(13) In this semiconductor device,
Each of the dummy patterns may be formed in a region surrounded by the wiring pattern.
[0019]
(14) In this semiconductor device,
The dummy pattern may be formed of the same material as the wiring pattern.
[0020]
(15) In this semiconductor device,
The mark may be a through hole formed in the dummy pattern.
[0021]
(16) In this semiconductor device,
The mark may be a through hole formed in the dummy pattern and the substrate.
[0022]
(17) In this semiconductor device,
The mark may be a through hole formed in the resin layer on the dummy pattern.
[0023]
(18) In this semiconductor device,
The pair of dummy patterns as a pair of first dummy patterns, and the mark as a first mark,
A pair of second dummy patterns;
The outer shape of the pair of second dummy patterns is a shape that is symmetrical with respect to each other with respect to a line that is a reference for symmetry of the pair of first dummy patterns,
The surface shape inside the outer shape of one of the second dummy patterns has a second mark,
The inside of the outer shape of the other second dummy pattern may have a surface shape different from the surface shape having the second mark.
[0024]
(19) In this semiconductor device,
The first mark is formed on one side with the symmetrical reference line as a boundary,
The second mark may be formed on the other side with the line serving as the reference of symmetry as a boundary.
[0025]
(20) In this semiconductor device,
The first and second marks may be different in size or shape.
[0026]
(21) A panel module according to the present invention includes the above semiconductor device,
A panel attached to the substrate and electrically connected to the wiring pattern;
Have
[0027]
(22) An electronic apparatus according to the present invention includes the semiconductor device.
[0028]
(23) A method of manufacturing a semiconductor device according to the present invention includes mounting a semiconductor chip on the wiring board,
The direction of the wiring board is recognized by the presence or absence of the mark.
[0029]
According to the present invention, since the direction of the wiring board is recognized, the occurrence of defective products can be reduced. Further, since the dummy pattern is formed on the substrate, the portion where the wiring pattern is not formed on the substrate is reduced, and the warpage and distortion of the substrate can be suppressed. Further, since the shape of the pair of dummy patterns is axisymmetric, asymmetric substrate warpage and distortion are unlikely to occur. The mark exists inside the outer shape of one dummy pattern and does not exist inside the outer shape of the other dummy pattern. However, since the outer shapes of both dummy patterns are axisymmetric, the warp and distortion of the asymmetric substrate Is unlikely to occur. From the above, it is possible to improve the reliability of mounting a semiconductor chip.
[0030]
(24) A method of manufacturing a semiconductor device according to the present invention includes mounting a semiconductor chip on the wiring board,
Recognizing the direction of the wiring board by the presence or absence of the first mark;
The wiring pattern and the semiconductor chip are aligned with reference to the first and second marks.
[0031]
According to the present invention, since the direction of the wiring board is recognized and the wiring pattern and the semiconductor chip are aligned, the occurrence of defective products can be reduced. Further, since the dummy pattern is formed on the substrate, the portion where the wiring pattern is not formed on the substrate is reduced, and the warpage and distortion of the substrate can be suppressed. Further, since the shape of the pair of dummy patterns is axisymmetric, asymmetric substrate warpage and distortion are unlikely to occur. The mark exists inside the outer shape of one dummy pattern and does not exist inside the outer shape of the other dummy pattern. However, since the outer shapes of both dummy patterns are axisymmetric, the warp and distortion of the asymmetric substrate Is unlikely to occur. From the above, it is possible to improve the reliability of mounting a semiconductor chip.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a wiring board according to the present embodiment.
[0033]
The wiring board has a substrate 10. The substrate 10 may be formed of a resin such as polyimide. The substrate 10 may have flexibility. The substrate 10 may be a tape, in which case the sprocket holes 12 may be formed in the substrate 10. The wiring board may be a TAB (Tape Automated Bonding) tape.
[0034]
A wiring pattern 20 is formed on the substrate 10. The wiring pattern 20 is electrically connected to other components (for example, the semiconductor chip 60 shown in FIG. 2 or the panel 80 shown in FIG. 3). The wiring pattern 20 may be formed of a conductive material (for example, metal) such as copper. The wiring pattern 20 may be formed by etching a metal foil attached to the substrate 10 or may be formed by evaporating a material on the substrate 10. Although one wiring pattern 20 is shown in FIG. 1, a plurality of wiring patterns 20 may be formed on the substrate 10.
[0035]
The wiring pattern 20 includes one or more groups of wirings (for example, the first to fourth groups of wirings 21 to 24). Each group of wirings is formed such that one end (hereinafter referred to as a first end) is aligned. The first tip may be a tip on the side electrically connected to a component (for example, the semiconductor chip 60 shown in FIG. 2) mounted on the substrate 10. The same applies to the wirings 22 to 24 of the second to fourth groups.
[0036]
At least one group of wires (for example, the first group of wires 21) has a straight line (the first tip is aligned) with the other tip (the tip opposite to the first tip; hereinafter referred to as the second tip). It may be formed so as to line up with a straight line different from the straight line). At least one group of wirings (for example, the second group of wirings 22) includes three or more wirings 26 having second ends arranged in a straight line, and at least one wiring having a second tip positioned at a position deviating from the straight lines. 28.
[0037]
At least one group of wirings (for example, the third or fourth group of wirings 23 and 24) has a second tip that is the second of the other groups of wirings (for example, the first and second groups of wirings 21 and 22). Two tips (three or more second tips arranged in a straight line) and wirings 30 and 32 arranged in a straight line may be included. Specifically, at least one group of wirings (for example, the third or fourth group of wirings 23 and 24) is the second tip (for example, 3 aligned in a straight line) of one group of wirings (for example, the first group of wirings 21). Wiring 30 aligned with one or more second tips) and second tips (three or more second tips aligned) of another group of wires (for example, second group of wires 22); Wiring 32 arranged in a straight line. At least one group of wirings (for example, the third or fourth group of wirings 23 and 24) may further include a wiring 34 in which the second tip is positioned so as not to be aligned.
[0038]
In at least one group of wirings (for example, the first group of wirings 21), the second ends aligned in a straight line are electrically connected to components (for example, the panel 80 shown in FIG. 3) attached to the substrate 10. It may be the tip. When the substrate 10 is a tape, the wiring pattern 20 may be formed so as to extend in the longitudinal direction of the substrate 10. The second ends aligned in a straight line may be aligned in the width direction of the substrate 10.
[0039]
A pair of dummy patterns 40 and 42 are formed on the substrate 10. Specifically, a pair of dummy patterns 40 and 42 are formed corresponding to one wiring pattern 20. Therefore, when a plurality of wiring patterns 20 are formed on the substrate 10, a pair of dummy patterns 40 and 42 are formed on the substrate 10 corresponding to each wiring pattern 20.
[0040]
Since the dummy pattern 40 is formed on the substrate 10, the portion of the substrate 10 where the wiring pattern 20 is not formed is reduced, and warpage and distortion of the substrate 10 can be suppressed. The outer shapes of the pair of dummy patterns 40 and 42 are shapes that are symmetrical with respect to each other with respect to the line L. The line L may extend in a direction along the longitudinal axis of the substrate 10. The line L may pass through the center of the substrate 10 in the width direction. Since the shape of the pair of dummy patterns 40 and 42 is axisymmetric, asymmetrical warpage and distortion of the substrate 10 are unlikely to occur. The outer shape of each of the dummy patterns 40 and 42 is not particularly limited, and may be a polygon, a circle, or a combination of these. The outer shapes of the pair of dummy patterns 40 and 42 may be formed at positions that are line-symmetric with respect to the line L. Each of the dummy patterns 40 and 42 may be formed in a region surrounded by the wiring pattern 20 (for example, the wirings 26 and 32). The dummy patterns 40 and 42 may be formed of the same material as the wiring pattern 20. The dummy patterns 40 and 42 may be formed simultaneously with the wiring pattern 20.
[0041]
The surface shape inside the outer shape of one dummy pattern 40 has a mark 44. The mark 44 may be a through hole formed in the dummy pattern 40, a through hole formed in the dummy pattern 40 and the substrate 10, or a resin layer (for example, a resist layer) on the dummy pattern 40. ) May be a through hole formed. The shape of the mark 44 is not particularly limited, and may be a circle, a polygon, or a combination of these.
[0042]
The inside of the outer shape of the other dummy pattern 42 has a surface shape different from the surface shape having the mark 44 (the surface shape inside the outer shape of the dummy pattern 40). A plurality of lines are formed inside the outer shape of the dummy pattern 42 shown in FIG. Alternatively, the dummy pattern 42 may be blank.
[0043]
At least the direction of the substrate 10 can be recognized by the mark 44. The mark 44 exists inside the outer shape of one dummy pattern 40 and does not exist inside the outer shape of the other dummy pattern 42. However, since the outer shapes of both the dummy patterns 40 and 42 are axisymmetric, they are asymmetric. Warp and distortion of the substrate 10 are difficult to occur.
[0044]
A pair of second dummy patterns 50 and 52 may be formed on the substrate 10 by using the pair of dummy patterns 40 and 42 as a pair of first dummy patterns. The external shape of the pair of second dummy patterns 50 and 52 may be a shape that is symmetrical with respect to each other with respect to a line L that is a reference for symmetry of the pair of first dummy patterns 40 and 42.
[0045]
With the mark 44 as the first mark, the inner surface shape of the outer shape of one second dummy pattern 50 may have the second mark 54. The inside of the outer shape of the other second dummy pattern 52 may have a surface shape different from the surface shape having the second mark 54. Regarding the other points, the contents described for the dummy patterns 40 and 42 and the first mark 44 are applicable to the second dummy patterns 50 and 52 and the second mark 54.
[0046]
According to the present embodiment, it is possible to align a component (for example, a semiconductor chip) mounted on the substrate 10 by using two marks (first and second marks 44 and 54). The first mark 44 may be formed on one side and the second mark 54 may be formed on the other side with the line L serving as a symmetrical reference of the pair of dummy patterns 40 and 42 as a boundary. In this case, since the distance between the first and second marks 44 and 54 is increased, the alignment accuracy is increased. The first and second marks 44, 54 may differ in size or shape. By doing so, it is possible to recognize the direction of the substrate 10.
[0047]
FIG. 2 is a diagram illustrating the semiconductor device according to the present embodiment. The semiconductor device illustrated in FIG. 2 includes the wiring substrate illustrated in FIG. 1 and the semiconductor chip 60 mounted on the substrate 10. When a plurality of wiring patterns 20 are formed on the substrate 10, the semiconductor device has a plurality of semiconductor chips 60.
[0048]
The semiconductor chip 60 is electrically connected to the wiring pattern 20. Specifically, the semiconductor chip 60 is electrically connected to the first tip side portion arranged in a straight line in one or more groups of wirings (for example, the first to fourth groups of wirings 21 to 24). It is connected to the. For the electrical connection, a method generally used in COF mounting can be applied. The first and second dummy patterns 40, 42, 50, 52 are not electrically connected to the semiconductor chip 60. The other contents relating to the semiconductor device correspond to the contents relating to the wiring board described above.
[0049]
The method for manufacturing a semiconductor device according to the present embodiment includes mounting the semiconductor chip 60 on the substrate 10. Then, the direction of the substrate 10 may be recognized by the presence or absence of the mark 44. Further, the alignment between the wiring pattern 20 and the semiconductor chip 60 may be performed with reference to the first and second marks 44 and 54.
[0050]
In this embodiment, since the direction of the substrate 10 is recognized and the wiring pattern 20 and the semiconductor chip 60 are aligned, the occurrence of defective products can be reduced. Further, as described above, since the warpage and distortion of the substrate 10 can be suppressed, the mounting reliability of the semiconductor chip 60 can be improved.
[0051]
FIG. 3 is a diagram showing a panel module according to the present embodiment. The panel module includes a semiconductor device 70 and a panel 80. The semiconductor device 70 includes a substrate 72 and a semiconductor chip 60. The substrate 72 may be obtained by punching the substrate 10 shown in FIG. The panel 80 may be a display panel (for example, a liquid crystal panel or an organic EL (Electroluminescence) panel). In that case, the panel module can be referred to as a display panel module. The substrate 72 is attached to the panel 80. The wiring pattern 20 formed on the substrate 72 is electrically connected to a wiring pattern (or lead) (not shown) formed on the panel 20.
[0052]
As an electronic apparatus having the above-described semiconductor device or panel module, a notebook personal computer 1000 is shown in FIG. 4, and a mobile phone 2000 is shown in FIG.
[0053]
The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram showing a wiring board according to an embodiment to which the present invention is applied.
FIG. 2 is a diagram illustrating a semiconductor device according to an embodiment to which the present invention is applied.
FIG. 3 is a diagram showing a panel module according to an embodiment to which the present invention is applied.
FIG. 4 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
FIG. 5 is a diagram showing an electronic apparatus according to an embodiment of the present invention.
[Explanation of symbols]
10 substrate 20 wiring pattern 40 dummy pattern 42 dummy pattern 44 mark 50 second dummy pattern 52 second dummy pattern 54 second mark 60 semiconductor chip 70 semiconductor device 80 panel

Claims (24)

A substrate,
A wiring pattern formed on the substrate;
A pair of dummy patterns formed on the substrate;
Have
The external shape of the pair of dummy patterns is a shape that is line-symmetric with each other,
The surface shape inside the outer shape of one of the dummy patterns has a mark,
The inside of the outer shape of the other dummy pattern is a wiring board having a surface shape different from the surface shape having the mark. The wiring board according to claim 1,
The wiring pattern is composed of one or more groups of wirings;
The wiring board in each group is formed such that one end is aligned in a straight line. In the wiring board according to claim 1 or 2,
Each of the dummy patterns is a wiring board formed in a region surrounded by the wiring pattern. The wiring board according to any one of claims 1 to 3,
The dummy pattern is a wiring board formed of the same material as the wiring pattern. In the wiring board according to any one of claims 1 to 4,
The wiring board is a through hole formed in the dummy pattern. In the wiring board according to any one of claims 1 to 4,
The mark is a wiring board which is a through hole formed in the dummy pattern and the substrate. In the wiring board according to any one of claims 1 to 4,
The wiring board is a through hole formed in the resin layer on the dummy pattern. The wiring board according to any one of claims 1 to 7,
The pair of dummy patterns as a pair of first dummy patterns, and the mark as a first mark,
A pair of second dummy patterns;
The outer shape of the pair of second dummy patterns is a shape that is symmetrical with respect to each other with respect to a line that is a reference for symmetry of the pair of first dummy patterns,
The surface shape inside the outer shape of one of the second dummy patterns has a second mark,
The wiring board having a surface shape different from the surface shape having the second mark on the inner side of the outer shape of the other second dummy pattern. The wiring board according to claim 8,
The first mark is formed on one side with the symmetrical reference line as a boundary,
A wiring board in which the second mark is formed on the other side with the line serving as a reference of symmetry as a boundary. In the wiring board according to claim 8 or 9,
The first and second marks are wiring boards that differ in size or shape. A substrate,
A wiring pattern formed on the substrate;
A pair of dummy patterns formed on the substrate;
A semiconductor chip mounted on the substrate and electrically connected to the wiring pattern;
Have
The external shape of the pair of dummy patterns is a shape that is line-symmetric with each other,
The surface shape inside the outer shape of one of the dummy patterns has a mark,
A semiconductor device in which the inside of the outer shape of the other dummy pattern has a surface shape different from the surface shape having the mark. The semiconductor device according to claim 11.
The dummy pattern is a semiconductor device that is not electrically connected to the semiconductor chip. The semiconductor device according to claim 11 or 12,
Each of the dummy patterns is a semiconductor device formed in a region surrounded by the wiring pattern. The semiconductor device according to any one of claims 11 to 13,
The dummy pattern is a semiconductor device formed of the same material as the wiring pattern. The semiconductor device according to any one of claims 11 to 14,
The semiconductor device in which the mark is a through hole formed in the dummy pattern. The semiconductor device according to any one of claims 11 to 14,
The semiconductor device in which the mark is a through hole formed in the dummy pattern and the substrate. The semiconductor device according to any one of claims 11 to 14,
The said mark is a semiconductor device which is a through-hole formed in the resin layer on the said dummy pattern. The semiconductor device according to any one of claims 11 to 17,
The pair of dummy patterns as a pair of first dummy patterns, and the mark as a first mark,
A pair of second dummy patterns;
The outer shape of the pair of second dummy patterns is a shape that is symmetrical with respect to each other with respect to a line that is a reference for symmetry of the pair of first dummy patterns,
The surface shape inside the outer shape of one of the second dummy patterns has a second mark,
A semiconductor device in which the inside of the outer shape of the other second dummy pattern has a surface shape different from the surface shape having the second mark. The semiconductor device according to claim 18.
The first mark is formed on one side with the symmetrical reference line as a boundary,
A semiconductor device in which the second mark is formed on the other side with the line serving as a reference of symmetry as a boundary. The semiconductor device according to claim 17 or 18,
The first and second marks are different semiconductor devices in size or shape. A semiconductor device according to any one of claims 11 to 20,
A panel attached to the substrate and electrically connected to the wiring pattern;
A panel module having. An electronic apparatus comprising the semiconductor device according to claim 11. Mounting a semiconductor chip on the wiring substrate according to claim 1,
A method of manufacturing a semiconductor device, wherein the direction of the wiring board is recognized by the presence or absence of the mark. Mounting a semiconductor chip on the wiring substrate according to claim 8,
Recognizing the direction of the wiring board by the presence or absence of the first mark;
A method of manufacturing a semiconductor device, wherein the wiring pattern and the semiconductor chip are aligned with reference to the first and second marks.

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