TW200633147A - Low-voltage, multiple thin-gate oxide and low-resistance gate electrode - Google Patents
Low-voltage, multiple thin-gate oxide and low-resistance gate electrodeInfo
- Publication number
- TW200633147A TW200633147A TW094145886A TW94145886A TW200633147A TW 200633147 A TW200633147 A TW 200633147A TW 094145886 A TW094145886 A TW 094145886A TW 94145886 A TW94145886 A TW 94145886A TW 200633147 A TW200633147 A TW 200633147A
- Authority
- TW
- Taiwan
- Prior art keywords
- low
- regions
- layer
- voltage
- peripheral
- Prior art date
Links
- 239000010410 layer Substances 0.000 abstract 5
- 230000002093 peripheral effect Effects 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 2
- 239000003989 dielectric material Substances 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/021,693 US7202125B2 (en) | 2004-12-22 | 2004-12-22 | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200633147A true TW200633147A (en) | 2006-09-16 |
TWI371829B TWI371829B (en) | 2012-09-01 |
Family
ID=36143766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094145886A TWI371829B (en) | 2004-12-22 | 2005-12-22 | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
Country Status (7)
Country | Link |
---|---|
US (2) | US7202125B2 (zh) |
EP (1) | EP1829103A1 (zh) |
JP (1) | JP4644258B2 (zh) |
KR (1) | KR100937896B1 (zh) |
CN (1) | CN101099236A (zh) |
TW (1) | TWI371829B (zh) |
WO (1) | WO2006069184A1 (zh) |
Families Citing this family (56)
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US7482223B2 (en) * | 2004-12-22 | 2009-01-27 | Sandisk Corporation | Multi-thickness dielectric for semiconductor memory |
US7202125B2 (en) * | 2004-12-22 | 2007-04-10 | Sandisk Corporation | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
JP4690747B2 (ja) * | 2005-03-09 | 2011-06-01 | 株式会社東芝 | 半導体記憶装置および半導体記憶装置の駆動方法 |
US7348256B2 (en) * | 2005-07-25 | 2008-03-25 | Atmel Corporation | Methods of forming reduced electric field DMOS using self-aligned trench isolation |
US7541240B2 (en) * | 2005-10-18 | 2009-06-02 | Sandisk Corporation | Integration process flow for flash devices with low gap fill aspect ratio |
EP2648220B1 (en) | 2006-06-30 | 2017-11-08 | Fujitsu Semiconductor Limited | Floating gate memory device with trench isolation and method for manufacturing thereof |
US7585746B2 (en) * | 2006-07-12 | 2009-09-08 | Chartered Semiconductor Manufacturing, Ltd. | Process integration scheme of SONOS technology |
KR101017506B1 (ko) * | 2007-05-03 | 2011-02-25 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 이의 제조 방법 |
US7955960B2 (en) * | 2007-03-22 | 2011-06-07 | Hynix Semiconductor Inc. | Nonvolatile memory device and method of fabricating the same |
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US7915124B2 (en) * | 2008-07-09 | 2011-03-29 | Sandisk Corporation | Method of forming dielectric layer above floating gate for reducing leakage current |
US7919809B2 (en) * | 2008-07-09 | 2011-04-05 | Sandisk Corporation | Dielectric layer above floating gate for reducing leakage current |
US8207036B2 (en) * | 2008-09-30 | 2012-06-26 | Sandisk Technologies Inc. | Method for forming self-aligned dielectric cap above floating gate |
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US9087913B2 (en) | 2012-04-09 | 2015-07-21 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
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US7202125B2 (en) * | 2004-12-22 | 2007-04-10 | Sandisk Corporation | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
-
2004
- 2004-12-22 US US11/021,693 patent/US7202125B2/en not_active Expired - Fee Related
-
2005
- 2005-12-19 CN CNA200580043383XA patent/CN101099236A/zh active Pending
- 2005-12-19 WO PCT/US2005/046448 patent/WO2006069184A1/en active Application Filing
- 2005-12-19 JP JP2007548445A patent/JP4644258B2/ja not_active Expired - Fee Related
- 2005-12-19 EP EP05855071A patent/EP1829103A1/en not_active Withdrawn
- 2005-12-19 KR KR1020077013278A patent/KR100937896B1/ko active IP Right Grant
- 2005-12-22 TW TW094145886A patent/TWI371829B/zh not_active IP Right Cessation
-
2007
- 2007-01-17 US US11/623,947 patent/US20070115725A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TWI371829B (en) | 2012-09-01 |
EP1829103A1 (en) | 2007-09-05 |
US20070115725A1 (en) | 2007-05-24 |
CN101099236A (zh) | 2008-01-02 |
KR100937896B1 (ko) | 2010-01-21 |
JP2008526029A (ja) | 2008-07-17 |
US20060134845A1 (en) | 2006-06-22 |
KR20070100250A (ko) | 2007-10-10 |
US7202125B2 (en) | 2007-04-10 |
WO2006069184A1 (en) | 2006-06-29 |
JP4644258B2 (ja) | 2011-03-02 |
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