TW200524054A - Methods of forming conductive structures including titanium-tungsten base layers and related structures - Google Patents

Methods of forming conductive structures including titanium-tungsten base layers and related structures Download PDF

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Publication number
TW200524054A
TW200524054A TW093122171A TW93122171A TW200524054A TW 200524054 A TW200524054 A TW 200524054A TW 093122171 A TW093122171 A TW 093122171A TW 93122171 A TW93122171 A TW 93122171A TW 200524054 A TW200524054 A TW 200524054A
Authority
TW
Taiwan
Prior art keywords
layer
conductive
system structure
electronic device
insulating layer
Prior art date
Application number
TW093122171A
Other languages
English (en)
Chinese (zh)
Inventor
J Daniel Mis
Dean Zehnder
Original Assignee
Unitive International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unitive International Ltd filed Critical Unitive International Ltd
Publication of TW200524054A publication Critical patent/TW200524054A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
TW093122171A 2003-07-25 2004-07-23 Methods of forming conductive structures including titanium-tungsten base layers and related structures TW200524054A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US49034003P 2003-07-25 2003-07-25
US50758703P 2003-10-01 2003-10-01
US10/879,411 US7244671B2 (en) 2003-07-25 2004-06-29 Methods of forming conductive structures including titanium-tungsten base layers and related structures

Publications (1)

Publication Number Publication Date
TW200524054A true TW200524054A (en) 2005-07-16

Family

ID=34118827

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093122171A TW200524054A (en) 2003-07-25 2004-07-23 Methods of forming conductive structures including titanium-tungsten base layers and related structures

Country Status (6)

Country Link
US (2) US7244671B2 (https=)
EP (1) EP1649508A2 (https=)
JP (1) JP2007500445A (https=)
KR (1) KR20060034716A (https=)
TW (1) TW200524054A (https=)
WO (1) WO2005013339A2 (https=)

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TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
US9711438B2 (en) 2010-03-25 2017-07-18 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US20190221446A1 (en) * 2018-01-12 2019-07-18 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

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US7455787B2 (en) * 2003-08-01 2008-11-25 Sunpower Corporation Etching of solar cell materials
TWI232571B (en) * 2004-04-09 2005-05-11 Advanced Semiconductor Eng Wafer structure and method for forming a redistribution layer therein
US7172786B2 (en) * 2004-05-14 2007-02-06 Hitachi Global Storage Technologies Netherlands B.V. Methods for improving positioning performance of electron beam lithography on magnetic wafers
DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
CN101138084B (zh) * 2004-10-29 2010-06-02 弗利普芯片国际有限公司 具有覆在聚合体层上的隆起的半导体器件封装
TWI258176B (en) * 2005-05-12 2006-07-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
AU2006311850B2 (en) * 2005-11-02 2011-06-16 Second Sight Medical Products, Inc. Implantable microelectronic device and method of manufacture
TWI294151B (en) * 2005-11-15 2008-03-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
JP4611943B2 (ja) * 2006-07-13 2011-01-12 Ｏｋｉセミコンダクタ株式会社 半導体装置
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
JP2008244134A (ja) * 2007-03-27 2008-10-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7973418B2 (en) * 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
JP2008300557A (ja) * 2007-05-30 2008-12-11 Mitsubishi Electric Corp 半導体装置
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
KR101483273B1 (ko) * 2008-09-29 2015-01-16 삼성전자주식회사 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들
JP5296567B2 (ja) * 2009-02-06 2013-09-25 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
DE112012003318T5 (de) * 2011-08-11 2014-04-30 Flipchip International, Llc Dünnfilm-Struktur für hochdichte Induktivitäten und Umverdrahtung bei Wafer-Level Packaging
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
KR101452587B1 (ko) * 2012-06-28 2014-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치
US8871634B2 (en) * 2012-08-30 2014-10-28 Intel Corporation Chip package incorporating interfacial adhesion through conductor sputtering
US9355906B2 (en) 2013-03-12 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9373594B2 (en) 2014-02-13 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Under bump metallization
US9401328B2 (en) 2014-12-22 2016-07-26 Stmicroelectronics S.R.L. Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure
US9859213B2 (en) * 2015-12-07 2018-01-02 Dyi-chung Hu Metal via structure
TWI744498B (zh) * 2018-03-05 2021-11-01 矽品精密工業股份有限公司 基板結構及其製法
US20220165694A1 (en) * 2020-11-26 2022-05-26 Mediatek Inc. Semiconductor structure
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US11990369B2 (en) 2021-08-20 2024-05-21 Applied Materials, Inc. Selective patterning with molecular layer deposition

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Publication number Priority date Publication date Assignee Title
US9711438B2 (en) 2010-03-25 2017-07-18 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
US20190221446A1 (en) * 2018-01-12 2019-07-18 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10651052B2 (en) 2018-01-12 2020-05-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Also Published As

Publication number Publication date
KR20060034716A (ko) 2006-04-24
WO2005013339A2 (en) 2005-02-10
US20070241460A1 (en) 2007-10-18
US20050020047A1 (en) 2005-01-27
JP2007500445A (ja) 2007-01-11
US7244671B2 (en) 2007-07-17
US7550849B2 (en) 2009-06-23
EP1649508A2 (en) 2006-04-26
WO2005013339A3 (en) 2005-04-28

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