KR20060034716A - 티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 - Google Patents

티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 Download PDF

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Publication number
KR20060034716A
KR20060034716A KR1020067001547A KR20067001547A KR20060034716A KR 20060034716 A KR20060034716 A KR 20060034716A KR 1020067001547 A KR1020067001547 A KR 1020067001547A KR 20067001547 A KR20067001547 A KR 20067001547A KR 20060034716 A KR20060034716 A KR 20060034716A
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KR
South Korea
Prior art keywords
layer
conductive
conductive structure
insulating layer
titanium
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KR1020067001547A
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English (en)
Korean (ko)
Inventor
다니엘 제이. 미스
딘 젠더
Original Assignee
유나이티브 인터내셔널 리미티드
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Publication of KR20060034716A publication Critical patent/KR20060034716A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
KR1020067001547A 2003-07-25 2004-07-16 티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 Withdrawn KR20060034716A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US49034003P 2003-07-25 2003-07-25
US60/490,340 2003-07-25
US50758703P 2003-10-01 2003-10-01
US60/507,587 2003-10-01

Publications (1)

Publication Number Publication Date
KR20060034716A true KR20060034716A (ko) 2006-04-24

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Family Applications (1)

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KR1020067001547A Withdrawn KR20060034716A (ko) 2003-07-25 2004-07-16 티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조

Country Status (6)

Country Link
US (2) US7244671B2 (https=)
EP (1) EP1649508A2 (https=)
JP (1) JP2007500445A (https=)
KR (1) KR20060034716A (https=)
TW (1) TW200524054A (https=)
WO (1) WO2005013339A2 (https=)

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KR100699659B1 (ko) * 2003-06-24 2007-03-23 마쯔시다덴기산교 가부시키가이샤 고분자 전해질형 연료전지
KR101452583B1 (ko) * 2012-01-24 2014-10-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 언더-범프 금속화층상의 크랙 스토퍼
KR101452587B1 (ko) * 2012-06-28 2014-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology

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DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
CN101138084B (zh) * 2004-10-29 2010-06-02 弗利普芯片国际有限公司 具有覆在聚合体层上的隆起的半导体器件封装
TWI258176B (en) * 2005-05-12 2006-07-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
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TWI294151B (en) * 2005-11-15 2008-03-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
JP4611943B2 (ja) * 2006-07-13 2011-01-12 Ｏｋｉセミコンダクタ株式会社 半導体装置
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
JP2008244134A (ja) * 2007-03-27 2008-10-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7973418B2 (en) * 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
JP2008300557A (ja) * 2007-05-30 2008-12-11 Mitsubishi Electric Corp 半導体装置
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
KR101483273B1 (ko) * 2008-09-29 2015-01-16 삼성전자주식회사 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들
JP5296567B2 (ja) * 2009-02-06 2013-09-25 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
US8759209B2 (en) 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
DE112012003318T5 (de) * 2011-08-11 2014-04-30 Flipchip International, Llc Dünnfilm-Struktur für hochdichte Induktivitäten und Umverdrahtung bei Wafer-Level Packaging
TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
US8871634B2 (en) * 2012-08-30 2014-10-28 Intel Corporation Chip package incorporating interfacial adhesion through conductor sputtering
US9355906B2 (en) 2013-03-12 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9373594B2 (en) 2014-02-13 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Under bump metallization
US9401328B2 (en) 2014-12-22 2016-07-26 Stmicroelectronics S.R.L. Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure
US9859213B2 (en) * 2015-12-07 2018-01-02 Dyi-chung Hu Metal via structure
US10651052B2 (en) 2018-01-12 2020-05-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
TWI744498B (zh) * 2018-03-05 2021-11-01 矽品精密工業股份有限公司 基板結構及其製法
US20220165694A1 (en) * 2020-11-26 2022-05-26 Mediatek Inc. Semiconductor structure
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US11990369B2 (en) 2021-08-20 2024-05-21 Applied Materials, Inc. Selective patterning with molecular layer deposition

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US6511901B1 (en) * 1999-11-05 2003-01-28 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
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KR100699659B1 (ko) * 2003-06-24 2007-03-23 마쯔시다덴기산교 가부시키가이샤 고분자 전해질형 연료전지
KR101452583B1 (ko) * 2012-01-24 2014-10-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 언더-범프 금속화층상의 크랙 스토퍼
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US9472524B2 (en) 2012-01-24 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Copper-containing layer on under-bump metallization layer
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
KR101452587B1 (ko) * 2012-06-28 2014-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치

Also Published As

Publication number Publication date
WO2005013339A2 (en) 2005-02-10
US20070241460A1 (en) 2007-10-18
US20050020047A1 (en) 2005-01-27
JP2007500445A (ja) 2007-01-11
US7244671B2 (en) 2007-07-17
US7550849B2 (en) 2009-06-23
EP1649508A2 (en) 2006-04-26
TW200524054A (en) 2005-07-16
WO2005013339A3 (en) 2005-04-28

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