TW200524054A - Methods of forming conductive structures including titanium-tungsten base layers and related structures - Google Patents

Methods of forming conductive structures including titanium-tungsten base layers and related structures Download PDF

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Publication number
TW200524054A
TW200524054A TW093122171A TW93122171A TW200524054A TW 200524054 A TW200524054 A TW 200524054A TW 093122171 A TW093122171 A TW 093122171A TW 93122171 A TW93122171 A TW 93122171A TW 200524054 A TW200524054 A TW 200524054A
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TW
Taiwan
Prior art keywords
layer
conductive
system structure
electronic device
insulating layer
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Application number
TW093122171A
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English (en)
Chinese (zh)
Inventor
J Daniel Mis
Dean Zehnder
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Unitive International Ltd
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Application filed by Unitive International Ltd filed Critical Unitive International Ltd
Publication of TW200524054A publication Critical patent/TW200524054A/zh

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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
TW093122171A 2003-07-25 2004-07-23 Methods of forming conductive structures including titanium-tungsten base layers and related structures TW200524054A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US49034003P 2003-07-25 2003-07-25
US50758703P 2003-10-01 2003-10-01
US10/879,411 US7244671B2 (en) 2003-07-25 2004-06-29 Methods of forming conductive structures including titanium-tungsten base layers and related structures

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TW200524054A true TW200524054A (en) 2005-07-16

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TW093122171A TW200524054A (en) 2003-07-25 2004-07-23 Methods of forming conductive structures including titanium-tungsten base layers and related structures

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US (2) US7244671B2 (enExample)
EP (1) EP1649508A2 (enExample)
JP (1) JP2007500445A (enExample)
KR (1) KR20060034716A (enExample)
TW (1) TW200524054A (enExample)
WO (1) WO2005013339A2 (enExample)

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TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
US9711438B2 (en) 2010-03-25 2017-07-18 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US20190221446A1 (en) * 2018-01-12 2019-07-18 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

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TWI232571B (en) * 2004-04-09 2005-05-11 Advanced Semiconductor Eng Wafer structure and method for forming a redistribution layer therein
US7172786B2 (en) * 2004-05-14 2007-02-06 Hitachi Global Storage Technologies Netherlands B.V. Methods for improving positioning performance of electron beam lithography on magnetic wafers
DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
WO2006050127A2 (en) * 2004-10-29 2006-05-11 Flipchip International, Llc Semiconductor device package with bump overlying a polymer layer
TWI258176B (en) * 2005-05-12 2006-07-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
EP1949437B2 (en) * 2005-11-02 2021-08-04 Second Sight Medical Products, Inc. Implantable microelectronic device and method of manufacture
TWI294151B (en) * 2005-11-15 2008-03-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
JP4611943B2 (ja) * 2006-07-13 2011-01-12 Okiセミコンダクタ株式会社 半導体装置
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
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EP1649508A2 (en) 2006-04-26
KR20060034716A (ko) 2006-04-24
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WO2005013339A3 (en) 2005-04-28
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