KR20060034716A - 티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 - Google Patents

티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 Download PDF

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KR20060034716A
KR20060034716A KR1020067001547A KR20067001547A KR20060034716A KR 20060034716 A KR20060034716 A KR 20060034716A KR 1020067001547 A KR1020067001547 A KR 1020067001547A KR 20067001547 A KR20067001547 A KR 20067001547A KR 20060034716 A KR20060034716 A KR 20060034716A
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layer
conductive
conductive structure
insulating layer
titanium
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Korean (ko)
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다니엘 제이. 미스
딘 젠더
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유나이티브 인터내셔널 리미티드
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Publication of KR20060034716A publication Critical patent/KR20060034716A/ko
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KR1020067001547A 2003-07-25 2004-07-16 티타늄-텅스텐 베이스층을 포함하는 도전 구조를 형성하는방법 및 관련 구조 Withdrawn KR20060034716A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US49034003P 2003-07-25 2003-07-25
US60/490,340 2003-07-25
US50758703P 2003-10-01 2003-10-01
US60/507,587 2003-10-01

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KR20060034716A true KR20060034716A (ko) 2006-04-24

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US (2) US7244671B2 (enExample)
EP (1) EP1649508A2 (enExample)
JP (1) JP2007500445A (enExample)
KR (1) KR20060034716A (enExample)
TW (1) TW200524054A (enExample)
WO (1) WO2005013339A2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699659B1 (ko) * 2003-06-24 2007-03-23 마쯔시다덴기산교 가부시키가이샤 고분자 전해질형 연료전지
KR101452583B1 (ko) * 2012-01-24 2014-10-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 언더-범프 금속화층상의 크랙 스토퍼
KR101452587B1 (ko) * 2012-06-28 2014-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology

Families Citing this family (33)

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Publication number Priority date Publication date Assignee Title
TWI229930B (en) * 2003-06-09 2005-03-21 Advanced Semiconductor Eng Chip structure
US7455787B2 (en) * 2003-08-01 2008-11-25 Sunpower Corporation Etching of solar cell materials
TWI232571B (en) * 2004-04-09 2005-05-11 Advanced Semiconductor Eng Wafer structure and method for forming a redistribution layer therein
US7172786B2 (en) * 2004-05-14 2007-02-06 Hitachi Global Storage Technologies Netherlands B.V. Methods for improving positioning performance of electron beam lithography on magnetic wafers
DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
WO2006050127A2 (en) * 2004-10-29 2006-05-11 Flipchip International, Llc Semiconductor device package with bump overlying a polymer layer
TWI258176B (en) * 2005-05-12 2006-07-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
EP1949437B2 (en) * 2005-11-02 2021-08-04 Second Sight Medical Products, Inc. Implantable microelectronic device and method of manufacture
TWI294151B (en) * 2005-11-15 2008-03-01 Advanced Semiconductor Eng Wafer structure and method for fabricating the same
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
JP4611943B2 (ja) * 2006-07-13 2011-01-12 Okiセミコンダクタ株式会社 半導体装置
TWI337386B (en) * 2007-02-16 2011-02-11 Chipmos Technologies Inc Semiconductor device and method for forming packaging conductive structure of the semiconductor device
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
JP2008244134A (ja) * 2007-03-27 2008-10-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7973418B2 (en) * 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
JP2008300557A (ja) * 2007-05-30 2008-12-11 Mitsubishi Electric Corp 半導体装置
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
KR101483273B1 (ko) * 2008-09-29 2015-01-16 삼성전자주식회사 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들
JP5296567B2 (ja) * 2009-02-06 2013-09-25 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
US8759209B2 (en) 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US9018750B2 (en) * 2011-08-11 2015-04-28 Flipchip International, Llc Thin film structure for high density inductors and redistribution in wafer level packaging
TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
US8871634B2 (en) * 2012-08-30 2014-10-28 Intel Corporation Chip package incorporating interfacial adhesion through conductor sputtering
US9355906B2 (en) 2013-03-12 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9373594B2 (en) * 2014-02-13 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Under bump metallization
US9401328B2 (en) 2014-12-22 2016-07-26 Stmicroelectronics S.R.L. Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure
US9859213B2 (en) * 2015-12-07 2018-01-02 Dyi-chung Hu Metal via structure
US10651052B2 (en) 2018-01-12 2020-05-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
TWI744498B (zh) * 2018-03-05 2021-11-01 矽品精密工業股份有限公司 基板結構及其製法
EP4033525A3 (en) * 2020-11-26 2023-08-02 Mediatek Inc. Semiconductor structure
US20220165694A1 (en) * 2020-11-26 2022-05-26 Mediatek Inc. Semiconductor structure
US11990369B2 (en) 2021-08-20 2024-05-21 Applied Materials, Inc. Selective patterning with molecular layer deposition

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8701184A (nl) 1987-05-18 1988-12-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JP2778127B2 (ja) * 1989-06-29 1998-07-23 日本電気株式会社 半導体装置の製造方法
JPH0555213A (ja) * 1991-08-23 1993-03-05 Hitachi Ltd 配線部材の形成方法
US5162257A (en) 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US5234149A (en) 1992-08-28 1993-08-10 At&T Bell Laboratories Debondable metallic bonding method
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
WO1996031905A1 (en) 1995-04-05 1996-10-10 Mcnc A solder bump structure for a microelectronic substrate
US5849641A (en) * 1997-03-19 1998-12-15 Lam Research Corporation Methods and apparatus for etching a conductive layer to improve yield
US6015505A (en) 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6511901B1 (en) * 1999-11-05 2003-01-28 Atmel Corporation Metal redistribution layer having solderable pads and wire bondable pads
JP2001244372A (ja) * 2000-03-01 2001-09-07 Seiko Epson Corp 半導体装置およびその製造方法
US6492197B1 (en) 2000-05-23 2002-12-10 Unitive Electronics Inc. Trilayer/bilayer solder bumps and fabrication methods therefor
US6319745B1 (en) * 2000-05-31 2001-11-20 International Business Machines Corporation Formation of charge-coupled-device with image pick-up array
US6674161B1 (en) * 2000-10-03 2004-01-06 Rambus Inc. Semiconductor stacked die devices
JP3526548B2 (ja) 2000-11-29 2004-05-17 松下電器産業株式会社 半導体装置及びその製造方法
US6462426B1 (en) 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
US20020121702A1 (en) 2001-03-01 2002-09-05 Siemens Dematic Electronics Assembly Systems, Inc. Method and structure of in-situ wafer scale polymer stud grid array contact formation
US6768210B2 (en) * 2001-11-01 2004-07-27 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
US6914332B2 (en) * 2002-01-25 2005-07-05 Texas Instruments Incorporated Flip-chip without bumps and polymer for board assembly
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699659B1 (ko) * 2003-06-24 2007-03-23 마쯔시다덴기산교 가부시키가이샤 고분자 전해질형 연료전지
KR101452583B1 (ko) * 2012-01-24 2014-10-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 언더-범프 금속화층상의 크랙 스토퍼
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US9472524B2 (en) 2012-01-24 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Copper-containing layer on under-bump metallization layer
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
KR101452587B1 (ko) * 2012-06-28 2014-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치

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