TW200414501A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW200414501A TW200414501A TW092136441A TW92136441A TW200414501A TW 200414501 A TW200414501 A TW 200414501A TW 092136441 A TW092136441 A TW 092136441A TW 92136441 A TW92136441 A TW 92136441A TW 200414501 A TW200414501 A TW 200414501A
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- semiconductor device
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01K—ANIMAL HUSBANDRY; CARE OF BIRDS, FISHES, INSECTS; FISHING; REARING OR BREEDING ANIMALS, NOT OTHERWISE PROVIDED FOR; NEW BREEDS OF ANIMALS
- A01K13/00—Devices for grooming or caring of animals, e.g. curry-combs; Fetlock rings; Tail-holders; Devices for preventing crib-biting; Washing devices; Protection against weather conditions or insects
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- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01K—ANIMAL HUSBANDRY; CARE OF BIRDS, FISHES, INSECTS; FISHING; REARING OR BREEDING ANIMALS, NOT OTHERWISE PROVIDED FOR; NEW BREEDS OF ANIMALS
- A01K29/00—Other apparatus for animal husbandry
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K13/00—Thermometers specially adapted for specific purposes
- G01K13/20—Clinical contact thermometers for use with humans or animals
- G01K13/25—Protective devices therefor, e.g. sleeves preventing contamination
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Description
200414501 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置,特別是關於在一個封裝體 搭載複數片半導體晶片的多晶片封裝體的半導體裝置。具 體上是關於,堆疊複數個SRAM( Static Random Ac eess Memory)等之記憶器,或與系統LSI組合層積的技術。 【先前技術】 隨著電子機器的高性能化、大容量化,在一個半導體 封裝體內配設複數片半導體晶片,高密度安裝的多晶片封 裝體(MCP)技術的開發正在快速進展。如此安裝複數片晶 片的技術,其具體方法有:在一片基板成平面狀排列複數 片晶片的方法;及將複數片晶片層積狀堆疊的方法。後者 的堆疊MCP的技術是,在線焊接設於要層積的晶片四邊 的晶片端子或焊墊時,使用間隔片等使要層積的晶片相互 間在高度方向也有一些寬度。同時也揭示,將焊墊配置在 晶片的相鄰接的兩邊,以堆疊複數片該晶片的技術(參照 ,例如,專利文獻1、專利文獻2)。 【專利文獻1】 特開平4 - 1 995 6 6號公報(第1圖) 【專利文獻2】 特開2001 - 196526號公報(第2圖) 本案發明人等在本案之前,爲了回應記憶器大容量化 的需求,注意到應該考量下述各點。亦即’在傳統的 SRAM晶片,因爲晶片上的焊墊是配置在晶片的相對向的 兩邊,因此在堆疊時,必須使用間隔片等使其有—S ® g -5- (2) (2)200414501 ,以確保焊接所需要的高度。因此,封裝體尺寸變大,能 堆疊的數目受到限制。 同時,要在一片晶片上搭載CPU、邏輯電路等的系統 LSI,附加大容量的SRAM晶片時,爲了提高系統LSI的 功能,而要將大容量的SRAM,跟搭載有CPU、邏輯電路 等的系統LSI晶片一起搭載在一片晶片上時’因SRAM晶 片的尺寸較其他晶片大,會招致晶片尺寸的增大。這會連 帶使封裝體尺寸的增大,造成起因於SRAM晶片的產能的 降低。而且,較之SRAM處理程序,系統LSI用處理程序 的配線基本上是多層配線,因此形成在SRAM上的配線層 將成無用之物。 如果改變方式,將SRAM晶片與系統LSI晶片分開, 而將兩晶片層積,因涉及傳統的SRAM晶片的大小或焊接 墊的配置位置,有時會發生無法堆疊的情事。 爲了解決這個問題,如上述專利文獻,將焊墊配置在 相鄰接的兩邊,將層積的晶片斜方向錯開搭載,便可以使 焊接較容易。 但是,使用上述專利文獻所揭示的技術,將SRAM晶 片相互層積時,本發明人等發覺到,有必要考慮位址焊墊 或資料輸入輸出用焊墊的配置位置。而且,考量低成本或 方便性,有必要考慮SRAM封裝體的焊墊位置,使其能夠 將SRAM堆疊在現用的SRAM封裝體。同時,將SRAM 晶片與系統L SI晶片堆疊時,也有必要適當安排焊墊位置 ,使堆疊較爲容易。 -6 - (3) (3)200414501 【發明內容】 本發明是有鑑於上述問題點而完成者,其目的在提供 ’能夠很容易層積系統LSI與SRAM,或使SRAM晶片間 的相互層積較容易的SRAM晶片。 本發明的上述及其他目的以及新穎的特徵,可以從本 說明書的記述及附圖獲得進一步的瞭解。 簡單說明本案所揭示的發明中,具代表性者的槪要如 下。 亦即’一種在具有四邊的半導體晶片上形成有:電路 方塊;從外部向上述電路方塊供應規定的位址信號的複數 個位址焊墊;及對上述電路方塊輸入或輸出資料的複數個 資料輸入輸出用焊墊的半導體裝置,上述複數個資料輸入 輸出用焊墊是,沿半導體晶片的第i邊配置,上述複數個 位址焊墊是,沿跟上述第1邊共有上述半導體晶片的一個 角的第2邊配置,上述第2邊不配置上述資料輸入輸出用焊 塾 〇 【實施方式】 〈實施例1 > 第1圖表示從上面所視的,本案發明第1實施例的半導 體晶片1 0中,堆疊複數片同一種類的晶片,錯開層積使其 不會與後述的層積有焊接墊的其他晶片重疊,搭載於T S 0 型的封裝體2的半導體裝置1,第2圖表示從下面看第i圖的 半導體裝置1,第3圖是沿第1圖的半導體裝置的A - A,面 (4) (4)200414501 的截面,以模式方式所示的截面圖。 在第1圖,半導體晶片10堆疊多片,該半導體晶片的 共有1個角.的兩邊配置有輸入輸出外部的信號用的焊接墊 3 〇,分別面向上述兩邊的邊不配置焊接墊。同時,如後述 ,焊接墊是在一邊配置位址焊墊,在另一邊配置資料輸入 輸出用焊墊,配置位址焊墊的一邊不設資料輸入輸出用焊 墊,配置資料輸入輸出用焊墊的一邊不設位址焊墊。同時 ,層積的各晶片的焊墊是,例如使用A II細線等的焊接線 1 1,將晶片的焊墊相互連接,然後,半導體裝置則以環氧 樹脂等加以封裝。層積在最下面的晶片的焊墊是經由焊接 線11,連接在半導體封裝體的端子12。半導體晶片是用黏 接帶TP連接在端子12,端子12則與可以使半導體晶片與 外部連接的外部端子連接,此外部端子配置有:位址端子 A0〜A22、/ UB、/ LB、寫入起動信號/ WE、/ OE、晶 片選擇信號051、/031、€32、/032等使半導體晶片上 的電路方塊動作的控制信號端子、資料輸入輸出用端子 DQ0〜DQ15供應電源用的VCC電源端子、VSS接地電位 用端子等。 雖不特別限定,但本實施例是將連接焊接墊的外部引 線端子配置在半導體封裝體的相對向的兩邊(短邊),其中 的一邊順序排列有 A 1〜A 7、A 1 8、A 1 9、/ L B、/ U B、 A22' CS2、/ WE、A21、A20、A8 〜A15,位址端子配置 在兩端側,控制信號端子配置在中央部。另一方面,雖不 特別限定,另一邊也順序排列有:AO、/ CS1、VSS、/ 200414501 (5) OE、DQO、DQ8、DQ1、DQ9、DQ2、DQ10、DQ3 、VCC、DQ4、DQ12、DQ5、DQ13、DQ6、DQ14、 DQ15、VSS、A16、A17,在邊端配置位址端子, 號端子或接地電位端子,並由其所夾,配置資料輸 用端子或電源端子。而,封裝體的長邊是配置成與 長邊方向同方向,配置資料輸入輸出用焊墊的邊與 的短邊平行,配置位址焊墊的邊與封裝體的長邊平 在第2圖,配置在半導體封裝體的相對向兩邊 端子中,配置資料輸入輸出用端子的邊的端子中 AO、A16、A17以外,亦即位址端子以外,是以不 導體晶片狀延伸。另一方面,面對配置AO、A 1 6、 及資料輸入輸出端子的邊的邊的端子,則以橫越半 片狀延伸。 第3圖表示,在TSOP型的封裝體的晶片搭載 置端子12,在其上面堆疊複數片本案的SRAM晶片 面圖。被堆疊的晶片的焊墊由焊接線1 1加以連接, ,亦即夾著黏接帶TP裝設在封裝體的引線框架的 焊墊,由焊接線連接在端子1 2。 本案的SRAM晶片是在相鄰接的兩邊配置焊墊 一邊配置位址焊墊,在另一邊配置資料輸入輸出用 藉此,可以不必改變現用的SRAM晶片的插腳位置 以搭載層積的複數片SRAM晶片。這時,搭載的 晶片也是在其一邊設位址焊墊,在另一邊設資料輸 用焊墊,配置位址焊墊的邊不設資料輸入輸出用焊 、DQ 1 1 DQ7、 控制信 入輸出 晶片的 封裝體 行。 的外部 ,除了 橫越半 A1 7、 導體晶 基板配 10的截 最下層 晶片的 ,在其 焊墊, ,便可 SRAM 入輸出 墊,便 -9 - (6) (6)200414501 可以取得封裝體端子與晶片焊墊的匹配性。同時,搭載複 數片同一 S R A Μ晶片時,將晶片斜方向錯開搭載,便可以 不必附設間隔片,能達成低成本化。同時,由於沒有間隔 片’層積的晶片的高度方向不受限制,可以堆疊很多片晶 片。 第4圖表示第1圖所示本案的SRAM晶片的布置的槪 要圖。在該圖表示,構成應用本發明的SRAM的電路方塊 中的主要者,這些可以藉由習知的半導體積體電路的製造 技術,形成在如單晶矽的1個半導體基板上。 雖不特別限定,該圖是將半導體晶片1 0十字狀分成長 邊方向及短邊方向,在各該領域配置複數個記憶器陣列 MA。在記憶器陣列MA的周邊配置:主字元驅動電路 MWD、感測放大器S a、X解碼器XDEC、Y解碼器YDEC 、輸入電路1C、輸出電路OC、電源電路行系救濟溶絲 XFUSE、列系救濟溶絲YFUSE等的周邊電路。記憶器陣 列MA與周邊電路的外側,於半導體晶片的邊配置測試用 的焊墊TEST或焊接墊。 在記憶器陣列MA配置有:複數條字元線WL、複數 條資料線DL、配置在字元線與資料線的交點的記憶單元 MC,第4圖以其中的1條字元線、1條資料線、及丨個記憶 單兀MC來代表。雖不特別限定,但記憶單元MC是由: 一對CMOS反相器的輸入與輸出相互連接而構成的正反器 (具有兩個p通道型負載MOS電晶體與兩個n通道型驅動 MOS電晶體);將上述正反器的兩個記憶節點選擇性連接 -10- (7) (7)200414501 到資料線的兩個η通道型轉送Μ Ο S電晶體,所構成。η 通道型MOS電晶體的閘電極連接字元線。字元線WL連 接在供應字元線的驅動電壓的副字元驅動電路SWD,副 字元驅動電路連接在選擇性驅動該等的主字元驅動電路 MWD。 配置在半導體晶片的相鄰接的兩邊的焊接墊是由,接 收位址信號的輸入的位址焊墊A ’ 0〜A ’ 2 2 ;接收控制信 號的輸入的控制信號焊墊;輸入輸出記憶單元的資料的資 料輸入輸出用焊墊D Q ’ 0〜D Q ’ 1 5 ;供應電源電壓或接地 電位用電源焊墊VCC’、接地電位用焊墊VSS’;輸入輸出 資料用的輸入輸出緩衝器(緩衝電路)3 6,所構成。此 SRAM進行從記憶單元MC讀出資訊或寫入時,從外部輸 入位址信號,生成列位址信號、行位址信號,分別輸入未 圖示的列位址緩衝電路、行位址緩衝電路,經由列解碼器 、行解碼器選擇記憶器陣列MA內的任意的記憶單元。而 ,輸入輸出資料在寫入動作時經由輸入輸出緩衝電路3 6輸 入,讀出動作時經由感測放大器SA、輸入輸出緩衝電路 36輸出。 在配置位址焊墊的長邊,成焊墊列配置位址焊墊與控 制信號焊墊,並考慮信號的流動方向,配置在與字元線垂 直的方向。另一方面,在配置資料輸入輸出甩焊墊的短邊 ,除了輸入輸出焊墊以外配置有電源焊墊或接地電位焊墊 等,配置在垂直於資料線的方向。同時,由配置焊墊的邊 所夾的角是不配置焊墊。這時,從角偶至焊墊的距離最好 -11 - (8) (8)200414501 是,焊墊的最小間距有輸出緩衝電路的布置寬度以上的間 距。 同時,在上述半導體晶片設有用以監視內部電壓、取 出內部電路方塊的中間信號,分析不良原因等的測試用焊 墊。此等測試用焊墊是藉由探針從晶片取出信號,不會被 焊接。本實施例是在面對配置位址焊墊與資料輸入輸出用 焊墊的邊的兩邊分別具備有測試用焊墊,但不限定如此, 可以依測試用焊墊的數目適度配置。 在本案的 SRAM,因爲配置位址焊墊的邊與資料線, 及配置資料輸入輸出用焊墊的邊與字元線分別成平行,因 此,沿著信號的流向配置焊墊,避免配線複雜化。同時, 將數目較資料輸入輸出用焊墊多的位址焊墊配置在半導體 晶片的長邊,因此,可以緩和配置焊墊的間距。而且,在 配置位址焊墊的邊的中央部配置輸入控制信號的焊墊,在 配置資料輸入輸出用焊墊的邊的端部配置控制信號焊墊與 接地電位焊墊,中央部配置電源焊墊,使其成爲跟上述 TSOP型的封裝體的匹配性良好的焊墊配置,藉此可以很 容易焊接端子與焊墊,同時,可以使用現有的SRAM封裝 體。除此之外,設有禁止配置焊墊領域,而從離開晶片角 部規定距離以上的部位配置焊墊,藉此使其較容易焊接。 再者,本實施例是在半導體晶片的長邊配置位址焊墊 ,在短邊配置資料輸入輸出用焊墊,但也可以在短邊配置 位址焊墊,在長邊配置資料輸入輸出用焊墊。同時,通常 是位址焊墊較資料輸入輸出用焊墊多,但如果無法在長邊 -12· (9) (9)200414501 或短邊完全配置位址焊墊時,也可以將位址焊墊配置在, 鄰接於配置資料輸入輸出用焊墊的另一邊。這時,配置資 料輸入輸出用焊墊的邊,資料輸入輸出用焊墊要成一群配 置,同時,位址焊墊也是要相互鄰接成一群配置,如此便 可以很容易搭機於現有的SRAM封裝體。而且,本實施例 是將焊墊列配置成一列,但也可以配置成兩列,交互交錯 配置成兩列也可以。 〈實施例2〉 第5圖係從上方所視的堆疊複數片本案第2實施例的半 導體 10,而搭載於 BGA(Boll Grid Array)型的 CSP(Chip Scale Package)的半導體裝置1的圖,第6圖係表示第5圖的 半導體裝置1的配線基板。第5圖是堆疊複數片與第4圖所 示的SRAM相同架構者,晶片的焊墊相互間用例如A u細 線等的焊接線1 1焊接。配置在封裝體的最下層的SRAM晶 片的焊墊,使用焊接線1 1焊接在封裝體的內部端子5 5〜 5 9 ’而用樹脂等加以封裝。封裝體的內部端子是由··位址 內部端子55、控制信號內部端子56、資料輸出輸入用端子 57、接地電位端子58、電源端子59所構成,雖不特別限定 ’但此等內部端子是配置在封裝體的相鄰接兩邊。其中的 一邊是在兩端排列位址內部端子,在中央部排列控制信號 內部端子’在另一邊的端部配置控制信號內部端子、接地 電位端子,在其所夾的部位配置資料輸出輸入端子與電源 端子。 -13- (10) (10)200414501 第6圖表示,從內部端子延伸的基板上部的配線5 2通 過通孔54,經過基板下部的配線60連接在焊錫球53,或從 通孔5 4直接連接在焊錫球5 3的情形。焊錫球5 3是排列成 GA(grid array)狀,各焊錫球具有對應內部端子的位址端 子、控制信號端子、資料輸入輸出用端子、接地電位端子 、電源端子的功能。 本實施例除了第1實施例所記載的效果之外,因爲在 封裝體的相鄰接兩邊設內部端子,因此可以很容易焊接本 案的晶片。同時,因爲將本案的SRAM搭載於BGA型的 CSP封裝體,因此可以將大容量的SRAM搭載於小且薄型 的封裝體。 〈實施例3〉 第7圖至第10圖表示將第3圖所示SRAM晶片13與系統 LSI 14晶片層積時的本案第3實施例。本實施例在第7圖表 示SRAM晶片較系統LSI晶片大時,第8圖表示SRAM晶 片與系統LSI晶片差不多同一大小時,第9圖表示SRAM 晶片較系統LSI晶片小時的情形。雖不特別限定,但系統 LSI晶片14是由:CPU 61、記憶器62、邏輯電路63、 CACHE用RAM 64、介面電路65等複數個電路方塊所構成 ,該等是由內部匯流排66連接在一起。在系統LSI晶片的 4邊配置與外部進行信號的輸入輸出的焊墊。配置在系統 LSI晶片的4邊的焊墊中,接在配置SRAM晶片13的焊墊 的兩邊的邊的焊墊’是藉由焊接線連接在SRAM晶片的焊 -14· (11) 200414501 墊。在層積的SRAM晶片與系統LSI晶片爲了設 SRAM晶片、系統LSI晶片均在鄰接的兩邊設有 焊墊,同時,對準兩晶片的相鄰接的兩邊分別共 而將兩片堆疊在一起。 第10圖表示本實施例的系統LSI與SRAM的 的槪略圖。從 CPU、ROM、LOGIC、CACHE 輸 信號或資料信號分別經由內部位址匯流排72、資 73輸入介面電路MCTL。輸入MCTL的信號經由 排72、資料匯流排73,輸入本案的SRAM。另一 SRAM輸出的資料信號則通過上述位址匯流排72 流排73輸入 MCTL,經由資料匯流排分別輸入 LOGIC等。本電路方塊圖中,有關CPU、ROM、 CACHE的部分是在上述的系統LSI晶片上進行 則在本案的SRAM晶片上進行。MCTL則由系統 與SRAM晶片雙方所具備。 本實施例是在搭載大容量SRAM的系統LSI 夠容易層積CPU、LOGIC、ROM等,而將大容. 晶片的焊接墊配置在相鄰接的兩邊,在其一邊配 墊,$另一邊配置資料輸入輸出用焊墊。如此, 數個CPU、LOGIC、CACHE、SRAM晶片等的系 想辦法安排焊接墊的配置位置的自由度較其他E SRAM晶片的焊墊配置位置,堆疊會比較容易。 如本實施例,在記憶晶片的相鄰接的兩邊中 置位址焊墊,在另一邊配置資料輸入輸出用焊墊 置介面, 介面用的 有的角, 電路方塊 出的位址 料匯流排 位址匯流 方面,從 、資料匯 ROM、 LOGIC、 :,SRAM L S I晶片 ,爲了能 量 SRAM 置位址焊 在搭載複 統 LSI, 晶片局的 的一邊配 ,而層積 -15- (12) (12)200414501 在系統L S I晶片’則不論邏輯晶片與記憶晶片的大小如何 ’均可容易層積,焊接。同時,在邏輯晶片與記憶晶片的 相鄰接的兩邊設置介面用的焊墊或緩衝電路,將與記憶晶 片的焊接墊連接的邏輯晶片的焊接墊,配置在共有邏輯晶 片的一個角的兩邊,使焊接或層積較容易。同時,如上述 ,在SRAM晶片的有焊墊的邊所夾的角設禁止配置焊墊領 域,便可以在如第7圖所示,系統 L SI晶片的焊墊較 SRAM晶片的焊墊小時,也能夠很容易焊接兩片晶片。 以上,依據發明的實施形態具體說明本發明人所完成 的發明,但本發明並非限定如上述實施形態,當然可以在 不脫離其主旨之範圍內作各種變更。 例如,本實施例係在SRAM晶片的相鄰接的兩邊具備 焊接墊,在一邊配置位址焊墊,在另一邊配置資料輸入輸 出用焊墊,但也能夠以 DRAM、SSRAM、SDRAM取代 SRAM,特別是,也能夠以通常於晶片4邊配置焊接墊的快 閃記憶器等其他記憶晶片來取代。同時,也可以將DRAM 相互堆疊,或SRAM與DRAM堆疊,取代SRAM相互間 堆疊。同時,搭載於系統LSI的記億器是SRAM,但搭載 於系統LSI的記憶器也可以不限定爲SRAM,也可以用其 他記憶晶片。同時,堆疊的晶片數在堆疊系統LSI與 SRAM時是兩層,SRAM相互堆疊時是也是兩層,但堆疊 安裝用半導體裝置可以是較兩層多的多層架構。 而且,本案是說明的堆疊 SRAM的封裝體,是以 TSOP型與BGA型的封裝體爲例子進行說明,但也可以搭 •16- (13) (13)200414501 載於QFP等的各種封裝體。 兹簡單說明,從本案所揭示的發明中具代表性者獲得 的效果如下。亦即,在層積複數片晶片的半導體裝置,因 爲在該晶片的相鄰接的兩邊配置焊接墊,在其一邊配置位 址焊墊’在其另一邊配置資料輸入輸出用焊墊,藉此可以 使層積晶片,及焊接很容易。 【圖式簡單說明】 第1圖係第1實施例之堆疊複數片本案的SRAM晶片, 將其安裝在 TSOP (Thin Small Outline Package)的上面圖 ο 第2圖係第1實施例之堆疊複數片本案的SRAM晶片, 將其安裝在TSOP的上面圖。 第3圖係第1實施例之堆疊複數片本案的S RAM晶片, 將其安裝在TSOP的截面圖。 第4圖係第1實施例之本案的SRAM晶片的槪要圖。 第5圖係第2實施例之堆疊複數片本案的SRAM晶片, 將其安裝在 CSP (Chip Scale Package)的上面圖。 第6圖係第2實施例之本案的CSP的基板配線的槪要 圖。 第7圖係令第3實施例之本案的SRAM晶片與較該 SRAM晶片小的系統LSI晶片層積的槪要圖。 第8圖係令第3實施例之本案的SRAM晶片與該SRAM 晶片差不多同一大小的系統LSI晶片層積的槪要圖。 -17- (14) 200414501 第9圖係令第3實施例之本案的SRAM晶片與較該 SRAM晶片大的系統LSI晶片層積的槪要圖。
SRAM晶片與系統LSI
第1 0圖係第3實施例之本案的 的電路塊的槪要圖。 [圖號說明] 1 :半導體裝置 2 :半導體封裝體 1 0、A、B :半導體晶片 1 1 :焊接線 12 :端子 13: SRAM 晶片 14 :系統LSI晶片 3 0 :焊接墊 3 6 :輸入輸出緩衝電路 5 1 :基板 5 2、6 0 :配線 5 3 :焊錫球配置位置 54 :通孔 5 5 :位址內部端子 5 6 :控制信號內部端子 5 7 :資料輸出輸入用端子 5 8 :接地電位端子 5 9 :電源端子 -18- (15)200414501 CS2 CS’2
61 : CPU
6 2 : 記憶、器 63 :邏輯) 64: CACHE 6 5 :介面電路-72 :位址匯流排 7 3 :資料匯流排 A0〜A22 :位址端子· A,0〜A,2 2 :位址焊墊- /UB、/ LB、/ WE、/ OE、CS1、/ CS1、CS2、/ :控制信號用端子 /UB,、/ LB,、/ WE,、/ OE,、CS,1、/ CS,1、 、/ C S ’ 2 :控制信號用焊墊 DQ0〜DQ15 :資料輸入輸出用端子 DQ’ 0〜DQ’ 15:資料輸入輸出用焊墊 VCC :電源端子 V C C,:電源焊墊) VSS :接地電位用端子 V S S,:接地電位用焊墊 TEST :測試用焊墊 TP :接合用黏接帶 MA :記憶器陣列 MWD :主字元驅動電路 SWD :副字元驅動電路
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XDEC :列解碼器 YDEC :行解碼器 MWDEC:主字元驅動電路 I/OC:輸入輸出電路 XFUSE : X救濟溶絲 YFUSE : Y救濟溶絲 W L :字元線 DL :資料線 C C :控制電路 V C :電源電路 YS :行開關 SA :感測放大器
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Claims (1)
- (1) 200414501 拾、申請專利範圍 1. 一種半導體裝置,在具有四邊的半導體晶片上形成 有:電路方塊;從外部向上述電路方塊供應規定的位址信 號的複數個位址焊墊;及對上述電路方塊輸入或輸出資料 的複數個資料輸入輸出用焊墊,其特徵爲, 上述複數個資料輸入輸出用焊墊是,沿半導體晶片的 第1邊配置, 上述複數個位址焊墊中的至少一個是,沿跟上述第1 邊共有上述半導體晶片的一個角的第2邊配置, 在面向上述第1邊的第3邊,與面向上述第2邊的第4邊 ,不配置上述複數個位址焊墊,及上述複數個資料輸入輸 出用焊墊。 2. 如申請專利範圍第1項所述之半導體裝置,其中 藉由焊接輸入或輸出上述半導體晶片外部的信號用的 焊墊,不配置在上述第3邊及上述第4邊, 不焊接的內部電路測試用焊墊配置在上述第3邊及上 述第4邊。 3. 如申請專利範圍第1項所述之半導體裝置,其中 令上述電路方塊動作所需要的控制信號及供應電源用 的焊墊是,配置在上述第1邊或第2邊,或者上部第1及第2 邊 要 需 所 作 e,w> 3M3 塊 方 路 電 述 上 令 置 配 不 則 邊 4 第 及 3 第 述 上 中 其 置 裝 導 半 之 述 所 用第 源圍 電範 應利 供專 及請 號申 信如 制 4 控 的 墊 焊 -21 - (2) (2)200414501 上述第2邊不配置上述複數個資料輸入輸出用焊墊。 5 ·如申請專利範圍第4項所述之半導體裝置,其中 上述第1邊不配置上述複數個位址焊墊。 6. —種半導體裝置,具備有,包含第1及第2晶片的層 積的複數片晶片,其特徵爲, 上述第1晶片是四方形的晶片,具備有,包含複數個 第1位址焊墊,與複數個資料輸入輸出用焊墊的複數個焊 接墊, 上述複數個資料輸入輸出用焊墊配置在上述四邊形的 晶片的第1邊, 上述複數個第1位址焊墊配置在,與上述第1邊共有上 述四邊形晶片的一個角的第2邊, 上述第2邊不配置上述複數個資料輸入輸出用焊墊, 面向上述第1邊的第3邊,與面向上述第2邊的第4邊, 不配置藉由焊接輸入或輸出外部的信號用的焊墊。 7. 如申請專利範圍第6項所述之半導體裝置,其中 上述第1晶片進一步具有,配置在上述第1邊的複數個 第2位址焊墊, 上述複數個第2位址焊墊的數目,較上述複數個資料 輸入輸出用焊墊的數目少。 8. 如申請專利範圍第7項所述之半導體裝置,其中 在上述第1邊,上述複數個資料輸入輸出用焊墊是相 互鄰接配置成爲一群,同時,上述複數個位址焊墊是相S 鄰接配置成爲一群。 -22- (3) (3)200414501 9.如申請專利範圍第6項所述之半導體裝置,其中 上述第1邊不配置輸入位址信號用的焊接墊。 10如申請專利範圍第9項所述之半導體裝置,其中 上述第1晶片包含,具有設在複數條字元線與複數條 位元線的交點的複數個記憶單元的記億體陣列, 上述複數條資料線配置在與上述第2邊平行的方向。 1 1 .如申請專利範圍第1 〇項所述之半導體裝置,其中 上述第1晶片呈長方形, 上述第2邊是上述第1晶片的長邊 12. 如申請專利範圍第1 1項所述之半導體裝置,其中 上述複數個焊接墊進一步含有:向上述第1晶片輸入 控制信號的控制信號用焊墊;及向上述第1晶片供應規定 的電位的電源用焊墊, 上述控制信號用焊墊,與上述電源用焊墊,配置在上 述第1及第2邊,不配置在上述第3及第4邊。 13. —種半導體裝置,申請專利範圍第6項之半導體裝 置進一步具有· 搭載上述複數片晶片的封裝體, 上述封裝體具有,與上述複數個焊接墊連接的複數個 外部引線端子’ 上述複數個外部引線端子配置在上述封裝體的對向的 兩邊。 14. 如申請專利範圍第13項所述之半導體裝置,其中 配置上述複數個資料輸入輸出用焊墊的邊,與上述封 •23- (4) (4)200414501 裝體的短邊方向平行。 15.如申請專利範圍第14項所述之半導體裝置,其中 上述複數個外部引線端子配置在上述封裝體的短邊。 1 6 ·如申請專利範圍第1 5項所述之半導體裝置,其中 配置在上述短邊中的一邊的上述複數個外部引線端子 ’分別連接在上述複數個資料輸入輸出用焊墊, 配置在上述短邊中的另一邊的上述複數個外部引線端 子,不連接在上述複數個資料輸入輸出用焊墊。 17. —種半導體裝置,申請專利範圍第6項之半導體裝 置進一步具有: 包含搭載上述複數片晶片的基板的封裝體, 上述基板具有,與上述第1晶片的上述複數個焊接墊 連接的焊墊, 配置在上述基板的焊墊配置在上述封裝體的相鄰接的 兩邊。 18. 如申請專利範圍第17項所述之半導體裝置,其中 上述複數個資料輸入輸出用焊墊,與沿上述基板的第 1邊配設的複數個焊墊連接, 在上述基板的跟上述第1邊不同的另一邊,不配設與 上述複數個資料輸入輸出用焊墊連接的焊墊。 19. 如申請專利範圍第6項所述之半導體裝置,其中 上述複數片晶片是同種的晶片, 上述複數片晶片是分別錯開層積,使配置各晶片的上 述第1與第2邊的上述複數個焊接墊,不與層積的其他晶片 -24- (5) (5)200414501 重疊。 2〇. 一種半導體裝置,層積有包含’具有4邊的記憶晶 片,及具有4邊的邏輯晶片的複數片晶片,其特徵爲, 上述記憶晶片是四邊形的晶片’具備有:包含複數個 第1位址焊墊、及複數個資料輸入輸出用焊墊的複數個第】 焊接墊, 上述複數個資料輸入輸出用'焊墊配置在上述記憶晶片 的第1邊, 上述複數個第1位址焊墊配置在’與上述第1邊共有上 述四邊形的晶片的一個角的第2邊’ 上述第2邊不配置上述複數個資料輸入輸出用焊墊, 在面對上述第1邊的第3邊,及面對上述第2邊的上述 第4邊,不配置藉由焊接輸入或輸出外部的信號用的焊墊 , 上述邏輯晶片是四邊形的晶片,4邊具有複數個第2焊 接塾, 配置於上述邏輯晶片上述複數個第2焊接墊中,與上 述記憶晶片連接的焊接墊,是配置在與上述邏輯晶片共有 〜個角的兩邊。 -25-
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JP2003005235A JP2004221215A (ja) | 2003-01-14 | 2003-01-14 | 半導体装置 |
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JP (1) | JP2004221215A (zh) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI381485B (zh) * | 2005-11-10 | 2013-01-01 | Renesas Electronics Corp | Semiconductor device manufacturing method and semiconductor device |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4970722B2 (ja) * | 2004-12-16 | 2012-07-11 | エルピーダメモリ株式会社 | 半導体チップ及び半導体メモリ装置 |
KR100630761B1 (ko) | 2005-08-23 | 2006-10-02 | 삼성전자주식회사 | 메모리 집적도가 다른 2개의 반도체 메모리 칩들을내장하는 반도체 멀티칩 패키지 |
JP4921937B2 (ja) * | 2006-11-24 | 2012-04-25 | 株式会社東芝 | 半導体集積回路 |
JP4489100B2 (ja) * | 2007-06-18 | 2010-06-23 | 株式会社東芝 | 半導体パッケージ |
US8058099B2 (en) * | 2007-06-28 | 2011-11-15 | Sandisk Technologies Inc. | Method of fabricating a two-sided die in a four-sided leadframe based package |
US8395246B2 (en) * | 2007-06-28 | 2013-03-12 | Sandisk Technologies Inc. | Two-sided die in a four-sided leadframe based package |
US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
JP2010021449A (ja) * | 2008-07-11 | 2010-01-28 | Toshiba Corp | 半導体装置 |
JP5581627B2 (ja) * | 2009-08-05 | 2014-09-03 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP2011061090A (ja) * | 2009-09-11 | 2011-03-24 | Elpida Memory Inc | 半導体装置及びこれを備える半導体パッケージ |
US20110193207A1 (en) * | 2010-02-09 | 2011-08-11 | Freescale Semiconductor, Inc | Lead frame for semiconductor die |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8653646B2 (en) | 2011-10-03 | 2014-02-18 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
US8659139B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
EP2766928A1 (en) | 2011-10-03 | 2014-08-20 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
JP5947904B2 (ja) | 2011-10-03 | 2016-07-06 | インヴェンサス・コーポレイション | 直交するウインドウを有するマルチダイ・ワイヤボンド・アセンブリのためのスタブ最小化 |
US8610260B2 (en) | 2011-10-03 | 2013-12-17 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
EP2764543A2 (en) | 2011-10-03 | 2014-08-13 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8405207B1 (en) | 2011-10-03 | 2013-03-26 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
EP2766931B1 (en) * | 2011-10-03 | 2021-12-01 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
KR101797079B1 (ko) | 2011-12-30 | 2017-11-14 | 삼성전자 주식회사 | Pop 구조의 반도체 패키지 |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
KR102043369B1 (ko) | 2012-11-21 | 2019-11-11 | 삼성전자주식회사 | 반도체 메모리 칩 및 이를 포함하는 적층형 반도체 패키지 |
JP6081229B2 (ja) | 2013-03-01 | 2017-02-15 | 株式会社東芝 | 半導体装置、無線装置、及び記憶装置 |
JP5535351B1 (ja) | 2013-03-01 | 2014-07-02 | 株式会社東芝 | 半導体装置 |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
KR102579877B1 (ko) | 2016-11-22 | 2023-09-18 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
EP3780095A1 (en) | 2019-06-14 | 2021-02-17 | Shenzhen Goodix Technology Co., Ltd. | Chip encapsulation structure and electronic device |
US11475940B2 (en) * | 2020-12-11 | 2022-10-18 | Micron Technology, Inc. | Semiconductor device layout for a plurality of pads and a plurality of data queue circuits |
US20230187348A1 (en) * | 2021-12-09 | 2023-06-15 | Texas Instruments Incorporated | Semiconductor fuse with multi-bond wire |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000315776A (ja) * | 1999-05-06 | 2000-11-14 | Hitachi Ltd | 半導体装置 |
US6605875B2 (en) * | 1999-12-30 | 2003-08-12 | Intel Corporation | Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size |
TW523890B (en) * | 2002-02-07 | 2003-03-11 | Macronix Int Co Ltd | Stacked semiconductor packaging device |
-
2003
- 2003-01-14 JP JP2003005235A patent/JP2004221215A/ja active Pending
- 2003-12-22 TW TW092136441A patent/TW200414501A/zh unknown
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2004
- 2004-01-14 KR KR1020040002534A patent/KR20040065176A/ko not_active Application Discontinuation
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI381485B (zh) * | 2005-11-10 | 2013-01-01 | Renesas Electronics Corp | Semiconductor device manufacturing method and semiconductor device |
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JP2004221215A (ja) | 2004-08-05 |
CN1518104A (zh) | 2004-08-04 |
KR20040065176A (ko) | 2004-07-21 |
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