TWI466247B - 三維封裝結構 - Google Patents

三維封裝結構 Download PDF

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TWI466247B
TWI466247B TW098100098A TW98100098A TWI466247B TW I466247 B TWI466247 B TW I466247B TW 098100098 A TW098100098 A TW 098100098A TW 98100098 A TW98100098 A TW 98100098A TW I466247 B TWI466247 B TW I466247B
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pads
row
pad
wafer
carrier
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TW098100098A
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TW201027682A (en
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Jen Chung Chen
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Nanya Technology Corp
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Priority to US12/406,969 priority patent/US7948073B2/en
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Description

三維封裝結構
本發明係有關於一種記憶體晶片的三維封裝結構，特別是有關於一種在晶片上具有z字型曲折(zigzag)排列的雙排式接墊佈局的三維封裝結構。
如熟習該項技藝者所知，記憶體晶片上的接墊(bond pad)常被設計在晶片中央區域且為雙排並列式的佈局，以配合傳統單晶粒封裝的窗型球柵陣列封裝(wBGA)技術。第1圖例示習知的窗型球柵陣列封裝結構的剖面示意圖。如第1圖所示，當晶面朝下，晶片上的雙排並列接墊，其分別為A接墊與B接墊，分別透過打金線及載板內的佈線與載板上相對應的A錫球與B錫球構成連接。此外，已知DDR-SDRAM記憶體晶片封裝體的各個錫球的訊號輸出位址(package ballout)均需符合美國電子工程設計發展聯合協會(JEDEC)所訂定的國際標準規格，而無法隨意的變動。
近年來，業界已發展出各種的DRAM堆疊封裝技術，例如，利用打線接合技術所做的三維封裝，應用在DRAM高容量模組。第2圖例示習知的三維封裝記憶體模組結構1的剖面示意圖。如第2圖所示，三維封裝記憶體模組結構1係在載板10上設置堆疊的晶片20及晶片30，其中，晶片20藉由膠層42固定在載板10上，而晶片30藉由膠層52固定在晶片20之上。晶片20上的A接墊22經由接合導線(bond wire)122連接至載板10的上表面10a上的轉接墊(bond finger)102，而晶片20上的B接墊24經由接合導線124連接至載板10的上表面10a上的轉接墊104，同樣的，晶片30上的A接墊32經由接合導線132連接至載板10的上表面10a上的轉接墊102，而晶片30上的B接墊34經由接合導線134連接至載板10的上表面10a上的轉接墊104。
如前所述，由於記憶體晶片封裝體的各個錫球的訊號輸出位址均需符合JEDEC國際標準規格，而無法隨意的變動，而原本晶片20上A接墊22應該連結對應至載板10的下表面10b上的A錫球，卻只能打線接合至載板10的上表面10a的左側的轉接墊102，原本晶片20上B接墊22應該連結對應至載板10的下表面10b上的B錫球，卻只能打線接合至載板10的上表面10a的右側的轉接墊104，故需再透過載板10內的內部繞線106及108才能將連接至轉接墊102及104的訊號位址連接到相對應的A錫球與B錫球位置。如此一來，使得內部繞線的長度增加許多，導致晶片的電性變差，其中，包括電阻、電感及電容都因此增加，這也使得訊號雜訊增加。
由此可知，目前該領域仍需要一種改良的DRAM堆疊封裝技術，以解決上述問題。
本發明提供一種新穎的三維封裝結構，其在晶片上具有z字型曲折(zigzag)排列的雙排式接墊佈局，可以大幅節省內部繞線長度，提升晶片性能。
根據本發明之較佳實施例，本發明提供一種三維封裝結構，包含有一載板；一第一晶片，疊設於該載板的一第一表面上，其中該第一晶片包含一第一排接墊及一第二排接墊，設於該第一晶片的一中央區域；一第二晶片，疊設於該第一晶片上；一第一轉接墊，沿著該載板的一第一邊，設於該載板的該第一表面上；一第二轉接墊，沿著該載板相對於該第一邊的一第二邊，設於該載板的該第一表面上；一第一接合導線，由該第一排接墊跨越過該第二排接墊，延伸至該第一轉接墊；以及一第二接合導線，由該第二排接墊跨越過該第一排接墊，延伸至該第二轉接墊。
根據本發明之另一較佳實施例，本發明提供一種半導體封裝結構，包含有一載板；一晶片，疊設於該載板的一第一表面上，其中該第一晶片包含一第一排接墊及一第二排接墊，設於該晶片的一中央區域；一第一轉接墊，沿該晶片一第一邊，設於該載板的該第一表面上；一第二轉接墊，沿該晶片一第二邊，設於該載板的該第一表面上，其中該第一邊相對該第二邊；一第一接合導線，由該第一排接墊跨越過該第二排接墊，延伸至該第一轉接墊；一第二接合導線，由該第二排接墊跨越過該第一排接墊，延伸至該第二轉接墊；一第一錫球，設於該載板的一第二表面上，且該第一錫球接近該第一轉接墊；以及一第二錫球，設於該載板的一第二表面上，且該第二錫球接近該第二轉接墊。
為了使　貴審查委員能更進一步了解本發明之特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅供參考與輔助說明用，並非用來對本發明加以限制者。
請參閱第3圖，其為依據本發明較佳實施例所繪示的三維封裝記憶體模組結構1a的剖面示意圖。如第3圖所示，本發明三維封裝記憶體模組結構1a在載板10上設置有堆疊的晶片200及晶片300，其中，晶片200及晶片300均為有雙排式接墊佈局，設於晶片200及晶片300的中央區域。晶片200藉由膠層42固定在載板10上，而晶片300藉由膠層52固定在晶片200之上。晶片200上第一排的A接墊202經由接合導線222，例如，金線，跨越第二排的B接墊204，連接至載板10的上表面10a上較接近A錫球的轉接墊104，而晶片200上的B接墊204經由接合導線224，跨越第一排的A接墊202，連接至載板10的上表面10a上較接近B錫球的轉接墊102，晶片300上的第一排的A接墊302經由接合導線322，跨越第二排的B接墊304，連接至載板10的上表面10a上較接近A錫球的轉接墊104，而晶片300上的B接墊304經由接合導線324，跨越第一排的A接墊302，連接至載板10的上表面10a上較接近B錫球的轉接墊102。其中，轉接墊102與轉接墊104係分別設於載板10的相反的兩側邊上。
本發明的主要技術特徵在於三維封裝記憶體模組結構1a的晶片200上的A接墊202，利用打線接合技術跨越過B接墊204上方，直接連結至載板10上較接近A錫球的轉接墊104，而晶片200上的B接墊204，利用打線接合技術越過A接墊202上方，直接連結至載板10上較接近B錫球的轉接墊102，而轉接墊102及104直接透過較短的內部繞線112及114即可電連接相應的B錫球及A錫球，如此即可有效縮短載板10內的內部繞線長度，改善晶片性能。
為了實現如第3圖中這樣的三維封裝記憶體模組結構1a，晶片200及300需有不同以往的接墊配置及佈局設計。請參閱第4圖，其為第3圖中三維封裝記憶體模組結構1a的上視圖，為簡化說明，僅以晶片300為例。如第4圖所示，晶片300上的A接墊302及B接墊304為z字型曲折(zigzag)排列的雙排式接墊佈局。同時，考慮到晶片尺寸的縮小，本發明將同排的接墊節距(pitch)縮短，而為了避免節距縮短造成打線接合時的交叉問題，載板10上的轉接墊向同一方向位移一小段距離，當打線接合時，先橫向平行將接合導線拉出，然後以一特定角度折彎後，再接合到轉接墊上，構成具有折角的接合導線322及324。
此外，過去為了載板工程的高產出率(high throughput)，轉接墊採用的是較大的設計尺寸，例如，250μm×150μm，本發明可配合晶片上z字型曲折排列的雙排式接墊佈局，同步將載板上的轉接墊設計成與晶片上雙排式接墊相同的節距，例如，250μm×70μm，以實現三維封裝時，成功的利用打線接合技術，達到縮短載板線路長度的目的。
請參閱第5圖，其依據本發明另一實施例所繪示的記憶體模組結構的上視圖，如第5圖所示，晶片300上的A接墊302及B接墊304同樣為z字型曲折排列的雙排式接墊佈局，其與第4圖中所繪示的結構差異在於，第5圖的接合導線322及324在打線接合時，不需要凹折，而是以平行直線方式，直接打線接合到相對應的轉接墊上。
綜上所述，本發明使載板的內部繞線長度減少約2至3倍，並改善電阻、電感及電容等封裝體的電性，使晶片的操作維持在最佳的效能，此外，藉此打線接合技術，應用於三維封裝將大大的節省封裝成本。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1．．．三維封裝記憶體模組結構
1a．．．三維封裝記憶體模組結構
10．．．載板
10a．．．上表面
10b．．．下表面
20．．．晶片
22A．．．接墊
24B．．．接墊
30．．．晶片
32A．．．接墊
34B．．．接墊
42．．．膠層
52．．．膠層
102．．．轉接墊
104．．．轉接墊
106．．．內部繞線
108．．．內部繞線
112．．．內部繞線
114．．．內部繞線
122．．．接合導線
124．．．接合導線
132．．．接合導線
134．．．接合導線
200．．．晶片
202A．．．接墊
204B．．．接墊
222．．．接合導線
224．．．接合導線
300．．．晶片
302A．．．接墊
304B．．．接墊
322．．．接合導線
324．．．接合導線
第1圖例示習知的窗型球柵陣列封裝結構的剖面示意圖。
第2圖例示習知的三維封裝記憶體模組結構的剖面示意圖。
第3圖為依據本發明較佳實施例所繪示的三維封裝記憶體模組結構的剖面示意圖。
第4圖為第3圖中三維封裝記憶體模組結構的上視圖。
第5圖為依據本發明另一實施例所繪示的記憶體模組結構的上視圖。
1a．．．三維封裝記憶體模組結構
10．．．載板
10a．．．上表面
10b．．．下表面
42．．．膠層
52．．．膠層
102．．．轉接墊
104．．．轉接墊
112．．．內部繞線
114．．．內部繞線
200．．．晶片
202A．．．接墊
204B．．．接墊
222．．．接合導線
224．．．接合導線
300．．．晶片
302A．．．接墊
304B．．．接墊
322．．．接合導線
324．．．接合導線

Claims (10)

  1. 一種三維封裝結構，包含有：一載板；一第一晶片，疊設於該載板的一第一表面上，其中該第一晶片包含一第一排接墊及一第二排接墊，設於該第一晶片的一中央區域；一第二晶片，直接疊設於該第一晶片上，其中該第一晶片與該第二晶片固定在該載板的同一側；一第一轉接墊，沿著該載板的一第一邊，設於該載板的該第一表面上，其中該第二排接墊相對較該第一排接墊靠近該第一轉接墊；一第二轉接墊，沿著該載板相對於該第一邊的一第二邊，設於該載板的該第一表面上，其中該第一排接墊相對較該第二排接墊靠近該第二轉接墊；一第一接合導線，由該第一排接墊跨越過該第二排接墊，延伸至該第一轉接墊；以及一第二接合導線，由該第二排接墊跨越過該第一排接墊，延伸至該第二轉接墊。
  2. 如申請專利範圍第1項所述之三維封裝結構，其中該第二晶片包含一第三排接墊及一第四排接墊。
  3. 如申請專利範圍第2項所述之三維封裝結構，其中該三維封裝結構另包含有一第三接合導線，由該第三排接墊跨越過該第四排接 墊，延伸至該第一轉接墊。
  4. 如申請專利範圍第3項所述之三維封裝結構，其中該三維封裝結構另包含有一第四接合導線，由該第四排接墊跨越過該第三排接墊，延伸至該第二轉接墊。
  5. 如申請專利範圍第1項所述之三維封裝結構，其中該三維封裝結構另包含有一第一錫球以及一第二錫球，設於該載板的一第二表面上，又其中該第一錫球接近該第一轉接墊，而該第二錫球接近該第二轉接墊。
  6. 如申請專利範圍第5項所述之三維封裝結構，其中該第一錫球經由一第一內部繞線與該第一轉接墊電連接，該第二錫球經由一第二內部繞線與該第二轉接墊電連接。
  7. 如申請專利範圍第1項所述之三維封裝結構，其中該第一排接墊及該第二排接墊為z字型曲折(zigzag)排列的雙排式接墊佈局。
  8. 一種半導體封裝結構，包含有：一載板；一晶片，其底面固定在該載板的一第一表面上，其中該晶片包含一第一排接墊及一第二排接墊設於該晶片的主動面的一中央區域上； 一第一轉接墊，沿該晶片一第一邊，設於該載板的該第一表面上；一第二轉接墊，沿該晶片一第二邊，設於該載板的該第一表面上，其中該第一邊相對該第二邊；一第一接合導線，由該第一排接墊跨越過該第二排接墊並延伸出該晶片的第一邊至該第一轉接墊；一第二接合導線，由該第二排接墊跨越過該第一排接墊並延伸出該晶片的第二邊至該第二轉接墊；一第一錫球，設於該載板的一第二表面上，且該第一錫球接近該第一轉接墊；以及一第二錫球，設於該載板的一第二表面上，且該第二錫球接近該第二轉接墊。
  9. 如申請專利範圍第8項所述之半導體封裝結構，其中該第一錫球經由一第一內部繞線與該第一轉接墊電連接，該第二錫球經由一第二內部繞線與該第二轉接墊電連接。
  10. 如申請專利範圍第8項所述之半導體封裝結構，其中該第一排接墊及該第二排接墊為z字型曲折(zigzag)排列的雙排式接墊佈局。
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