SG91363A1 - Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer - Google Patents

Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer

Info

Publication number
SG91363A1
SG91363A1 SG200103140A SG200103140A SG91363A1 SG 91363 A1 SG91363 A1 SG 91363A1 SG 200103140 A SG200103140 A SG 200103140A SG 200103140 A SG200103140 A SG 200103140A SG 91363 A1 SG91363 A1 SG 91363A1
Authority
SG
Singapore
Prior art keywords
integrated circuit
stop layer
etch stop
contact structures
making metallization
Prior art date
Application number
SG200103140A
Other languages
English (en)
Inventor
Alain Blosse
Sanjay Thedki
Jianmin Qiao
Yitzhak Gilboa
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of SG91363A1 publication Critical patent/SG91363A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
SG200103140A 2000-06-15 2001-05-25 Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer SG91363A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/593,968 US6399512B1 (en) 2000-06-15 2000-06-15 Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer

Publications (1)

Publication Number Publication Date
SG91363A1 true SG91363A1 (en) 2002-09-17

Family

ID=24376957

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200103140A SG91363A1 (en) 2000-06-15 2001-05-25 Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer

Country Status (6)

Country Link
US (1) US6399512B1 (de)
EP (1) EP1164637A3 (de)
JP (1) JP3730539B2 (de)
KR (1) KR100421155B1 (de)
SG (1) SG91363A1 (de)
TW (1) TW516106B (de)

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US7183222B2 (en) * 2000-09-01 2007-02-27 Cypress Semiconductor Corporation Dual damascene structure and method of making
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US6740592B1 (en) * 2001-12-03 2004-05-25 Taiwan Semiconductor Manufacturing Company Shallow trench isolation scheme for border-less contact process
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DE10234165B4 (de) * 2002-07-26 2008-01-03 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Füllen eines Grabens, der in einem Substrat gebildet ist, mit einem isolierenden Material
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US7238588B2 (en) * 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US7648886B2 (en) * 2003-01-14 2010-01-19 Globalfoundries Inc. Shallow trench isolation process
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DE10311691A1 (de) * 2003-03-17 2004-10-07 Infineon Technologies Ag Herstellungsverfahren für eine Halbleiterstruktur
US6921709B1 (en) 2003-07-15 2005-07-26 Advanced Micro Devices, Inc. Front side seal to prevent germanium outgassing
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
US7378744B2 (en) * 2004-05-10 2008-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
US7067409B2 (en) * 2004-05-10 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
US7235489B2 (en) * 2004-05-21 2007-06-26 Agere Systems Inc. Device and method to eliminate shorting induced by via to metal misalignment
JP4567396B2 (ja) * 2004-08-10 2010-10-20 セイコーインスツル株式会社 半導体集積回路装置
KR100613392B1 (ko) * 2004-12-23 2006-08-17 동부일렉트로닉스 주식회사 자기 정렬 콘택홀 형성 방법
TW200628877A (en) * 2005-02-04 2006-08-16 Prime View Int Co Ltd Method of manufacturing optical interference type color display
US7776729B2 (en) * 2006-11-30 2010-08-17 Intel Corporation Transistor, method of manufacturing same, etchant for use during manufacture of same, and system containing same
US8679970B2 (en) * 2008-05-21 2014-03-25 International Business Machines Corporation Structure and process for conductive contact integration
JP5377489B2 (ja) 2008-07-18 2013-12-25 株式会社アルバック Ｃｕ配線膜の形成方法
JP5522377B2 (ja) * 2009-03-05 2014-06-18 Ｔｄｋ株式会社 貫通電極の形成方法、及び半導体基板
US8282846B2 (en) * 2010-02-27 2012-10-09 National Semiconductor Corporation Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad from corrosion and method of forming the metal interconnect structure
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Also Published As

Publication number Publication date
US6399512B1 (en) 2002-06-04
EP1164637A3 (de) 2006-09-06
JP2002016140A (ja) 2002-01-18
JP3730539B2 (ja) 2006-01-05
KR100421155B1 (ko) 2004-03-03
TW516106B (en) 2003-01-01
KR20010113011A (ko) 2001-12-24
EP1164637A2 (de) 2001-12-19

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