SG76592A1 - Semiconductor integrated circuit device and process for manufacturing the same - Google Patents

Semiconductor integrated circuit device and process for manufacturing the same

Info

Publication number
SG76592A1
SG76592A1 SG1999001030A SG1999001030A SG76592A1 SG 76592 A1 SG76592 A1 SG 76592A1 SG 1999001030 A SG1999001030 A SG 1999001030A SG 1999001030 A SG1999001030 A SG 1999001030A SG 76592 A1 SG76592 A1 SG 76592A1
Authority
SG
Singapore
Prior art keywords
manufacturing
same
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
SG1999001030A
Other languages
English (en)
Inventor
Yasuhiro Taniguchi
Shoji Shukuri
Kenichi Kuroda
Shuji Ikeda
Takashi Hashimoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of SG76592A1 publication Critical patent/SG76592A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG1999001030A 1998-03-16 1999-02-25 Semiconductor integrated circuit device and process for manufacturing the same SG76592A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10065115A JP2978467B2 (ja) 1998-03-16 1998-03-16 半導体集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
SG76592A1 true SG76592A1 (en) 2000-11-21

Family

ID=13277579

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1999001030A SG76592A1 (en) 1998-03-16 1999-02-25 Semiconductor integrated circuit device and process for manufacturing the same

Country Status (6)

Country Link
US (2) US6211003B1 (zh)
JP (1) JP2978467B2 (zh)
KR (1) KR100564180B1 (zh)
CN (2) CN1516259A (zh)
SG (1) SG76592A1 (zh)
TW (1) TW407307B (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3538081B2 (ja) * 1999-08-24 2004-06-14 松下電器産業株式会社 半導体装置の製造方法
JP4142228B2 (ja) * 2000-02-01 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置
US6399465B1 (en) * 2000-02-24 2002-06-04 United Microelectronics Corp. Method for forming a triple well structure
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6376870B1 (en) * 2000-09-08 2002-04-23 Texas Instruments Incorporated Low voltage transistors with increased breakdown voltage to substrate
JP4053232B2 (ja) * 2000-11-20 2008-02-27 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP4530527B2 (ja) * 2000-12-08 2010-08-25 ルネサスエレクトロニクス株式会社 スタティック型半導体記憶装置
JP2002198439A (ja) * 2000-12-26 2002-07-12 Sharp Corp 半導体装置および携帯電子機器
US6586817B1 (en) * 2001-05-18 2003-07-01 Sun Microsystems, Inc. Device including a resistive path to introduce an equivalent RC circuit
US6489224B1 (en) * 2001-05-31 2002-12-03 Sun Microsystems, Inc. Method for engineering the threshold voltage of a device using buried wells
US6514810B1 (en) * 2001-08-01 2003-02-04 Texas Instruments Incorporated Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
US6908859B2 (en) * 2001-10-12 2005-06-21 Texas Instruments Incorporated Low leakage power transistor and method of forming
US20030134479A1 (en) * 2002-01-16 2003-07-17 Salling Craig T. Eliminating substrate noise by an electrically isolated high-voltage I/O transistor
KR100466193B1 (ko) * 2002-07-18 2005-01-13 주식회사 하이닉스반도체 반도체 메모리 소자의 제조 방법
JP4160550B2 (ja) 2004-10-29 2008-10-01 株式会社東芝 不揮発性半導体記憶装置
JP5034945B2 (ja) * 2005-08-18 2012-09-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
JP5222540B2 (ja) * 2007-05-15 2013-06-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5259246B2 (ja) 2008-05-09 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2009283867A (ja) * 2008-05-26 2009-12-03 Toshiba Corp 半導体装置
JP4602441B2 (ja) * 2008-06-16 2010-12-22 株式会社東芝 不揮発性半導体記憶装置
US7868423B2 (en) * 2008-11-12 2011-01-11 International Business Machines Corporation Optimized device isolation
JP5711033B2 (ja) * 2011-04-12 2015-04-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP6246076B2 (ja) * 2014-06-05 2017-12-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
KR20160001913A (ko) * 2014-06-27 2016-01-07 에스케이하이닉스 주식회사 전력용 전자 소자
US9773733B2 (en) * 2015-03-26 2017-09-26 Mie Fujitsu Semiconductor Limited Semiconductor device
JP2017054966A (ja) * 2015-09-10 2017-03-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9633734B1 (en) * 2016-07-14 2017-04-25 Ememory Technology Inc. Driving circuit for non-volatile memory
US9831134B1 (en) * 2016-09-28 2017-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device having deep wells
KR20230165567A (ko) * 2022-05-27 2023-12-05 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2965783B2 (ja) * 1991-07-17 1999-10-18 三菱電機株式会社 半導体装置およびその製造方法
JP2682425B2 (ja) * 1993-12-24 1997-11-26 日本電気株式会社 半導体装置の製造方法
JP3601612B2 (ja) 1994-09-22 2004-12-15 富士通株式会社 半導体装置及びその製造方法
JP3101515B2 (ja) 1995-01-20 2000-10-23 三洋電機株式会社 Ｃｍｏｓ半導体装置の製造方法
JP2746175B2 (ja) 1995-02-28 1998-04-28 日本電気株式会社 高耐圧半導体装置
US5753956A (en) * 1996-01-11 1998-05-19 Micron Technology, Inc. Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry
JPH09293788A (ja) 1996-04-25 1997-11-11 Nec Corp 半導体装置の製造方法
JP3529549B2 (ja) 1996-05-23 2004-05-24 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US20010021551A1 (en) 2001-09-13
KR19990077856A (ko) 1999-10-25
US6211003B1 (en) 2001-04-03
TW407307B (en) 2000-10-01
JP2978467B2 (ja) 1999-11-15
CN1238557A (zh) 1999-12-15
KR100564180B1 (ko) 2006-03-29
US6387744B2 (en) 2002-05-14
CN1516259A (zh) 2004-07-28
JPH11261021A (ja) 1999-09-24
CN1142586C (zh) 2004-03-17

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