SG11202010376WA - Multiple-stack three-dimensional memory device and fabrication method thereof - Google Patents
Multiple-stack three-dimensional memory device and fabrication method thereofInfo
- Publication number
- SG11202010376WA SG11202010376WA SG11202010376WA SG11202010376WA SG11202010376WA SG 11202010376W A SG11202010376W A SG 11202010376WA SG 11202010376W A SG11202010376W A SG 11202010376WA SG 11202010376W A SG11202010376W A SG 11202010376WA SG 11202010376W A SG11202010376W A SG 11202010376WA
- Authority
- SG
- Singapore
- Prior art keywords
- stack
- memory device
- fabrication method
- dimensional memory
- dimensional
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/097432 WO2020019301A1 (en) | 2018-07-27 | 2018-07-27 | Multiple-stack three-dimensional memory device and fabrication method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11202010376WA true SG11202010376WA (en) | 2020-11-27 |
Family
ID=64789406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11202010376WA SG11202010376WA (en) | 2018-07-27 | 2018-07-27 | Multiple-stack three-dimensional memory device and fabrication method thereof |
Country Status (10)
Country | Link |
---|---|
US (3) | US10868031B2 (zh) |
JP (1) | JP7118172B2 (zh) |
KR (2) | KR102585801B1 (zh) |
CN (2) | CN111564450B (zh) |
AU (1) | AU2018433803B2 (zh) |
BR (1) | BR112020023959A2 (zh) |
DE (1) | DE112018007788T5 (zh) |
SG (1) | SG11202010376WA (zh) |
TW (1) | TWI705557B (zh) |
WO (1) | WO2020019301A1 (zh) |
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DE112018007788T5 (de) | 2018-07-27 | 2021-04-15 | Yangtze Memory Technologies Co., Ltd. | Dreidimensionale speichervorrichtung mit mehreren stapeln und verfahren zu ihrer herstellung |
KR102650421B1 (ko) * | 2019-02-12 | 2024-03-25 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
JP7353374B2 (ja) * | 2019-03-18 | 2023-09-29 | 長江存儲科技有限責任公司 | 三次元メモリデバイスにおける高κ誘電体層およびこれを形成するための方法 |
KR102689647B1 (ko) | 2019-06-20 | 2024-07-30 | 삼성전자주식회사 | 확장부를 갖는 채널 구조체를 포함하는 3차원 플래시 메모리 소자 |
JP2021048372A (ja) * | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置の製造方法 |
WO2021051383A1 (en) * | 2019-09-20 | 2021-03-25 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having multi-deck structure and methods for forming the same |
CN110800108B (zh) | 2019-09-20 | 2021-09-14 | 长江存储科技有限责任公司 | 具有多堆栈结构的三维存储器件及其形成方法 |
US11527549B2 (en) * | 2019-10-04 | 2022-12-13 | SK Hynix Inc. | Memory device and method of manufacturing the same |
CN111180455B (zh) * | 2020-01-02 | 2022-11-29 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
CN111180344B (zh) * | 2020-01-02 | 2021-12-07 | 长江存储科技有限责任公司 | 三维堆叠结构及制备方法 |
CN111403408B (zh) * | 2020-03-23 | 2023-06-30 | 长江存储科技有限责任公司 | 一种半导体器件制作方法和用该方法制成的半导体器件 |
US11081443B1 (en) | 2020-03-24 | 2021-08-03 | Sandisk Technologies Llc | Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same |
WO2021195997A1 (en) | 2020-03-31 | 2021-10-07 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and method for forming the same |
CN111430361B (zh) * | 2020-04-09 | 2023-07-25 | 长江存储科技有限责任公司 | 一种3d nand存储器件的制造方法 |
CN113555370B (zh) * | 2020-04-24 | 2024-09-06 | 长江存储科技有限责任公司 | 具有漏极选择栅切割结构的三维存储器件及其形成方法 |
US12048151B2 (en) | 2020-05-27 | 2024-07-23 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
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CN112585754B (zh) * | 2020-05-27 | 2024-07-19 | 长江存储科技有限责任公司 | 用于形成三维存储器件的方法 |
US11963349B2 (en) | 2020-05-27 | 2024-04-16 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory devices with backside source contacts |
CN111799273A (zh) * | 2020-06-11 | 2020-10-20 | 长江存储科技有限责任公司 | 一种半导体器件及其制造方法 |
US11856781B2 (en) * | 2020-07-22 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
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CN112768454B (zh) * | 2021-01-21 | 2022-08-09 | 长江存储科技有限责任公司 | 三维存储器的擦除操作方法 |
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US10971507B2 (en) * | 2018-02-15 | 2021-04-06 | Sandisk Technologies Llc | Three-dimensional memory device containing through-memory-level contact via structures |
US10854627B1 (en) * | 2018-06-29 | 2020-12-01 | Sandisk Technologies Llc | Three-dimensional memory device containing a capped insulating source line core and method of making the same |
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2018
- 2018-07-27 DE DE112018007788.8T patent/DE112018007788T5/de active Pending
- 2018-07-27 CN CN202010428927.0A patent/CN111564450B/zh active Active
- 2018-07-27 CN CN201880001660.8A patent/CN109075174B/zh active Active
- 2018-07-27 KR KR1020217004089A patent/KR102585801B1/ko active IP Right Grant
- 2018-07-27 BR BR112020023959-3A patent/BR112020023959A2/pt not_active Application Discontinuation
- 2018-07-27 KR KR1020237033266A patent/KR20230144656A/ko not_active Application Discontinuation
- 2018-07-27 AU AU2018433803A patent/AU2018433803B2/en active Active
- 2018-07-27 JP JP2020564060A patent/JP7118172B2/ja active Active
- 2018-07-27 SG SG11202010376WA patent/SG11202010376WA/en unknown
- 2018-07-27 WO PCT/CN2018/097432 patent/WO2020019301A1/en active Application Filing
- 2018-09-10 US US16/126,919 patent/US10868031B2/en active Active
- 2018-10-17 TW TW107136481A patent/TWI705557B/zh active
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2020
- 2020-10-16 US US17/072,958 patent/US11968832B2/en active Active
-
2024
- 2024-02-07 US US18/435,294 patent/US20240179911A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
JP7118172B2 (ja) | 2022-08-15 |
CN109075174A (zh) | 2018-12-21 |
US20210043651A1 (en) | 2021-02-11 |
JP2021524157A (ja) | 2021-09-09 |
BR112020023959A2 (pt) | 2021-02-23 |
US20240179911A1 (en) | 2024-05-30 |
CN111564450B (zh) | 2021-05-25 |
KR102585801B1 (ko) | 2023-10-05 |
US10868031B2 (en) | 2020-12-15 |
DE112018007788T5 (de) | 2021-04-15 |
TWI705557B (zh) | 2020-09-21 |
WO2020019301A1 (en) | 2020-01-30 |
KR20230144656A (ko) | 2023-10-16 |
AU2018433803B2 (en) | 2021-12-02 |
AU2018433803A1 (en) | 2020-10-15 |
KR20210030434A (ko) | 2021-03-17 |
CN109075174B (zh) | 2020-06-26 |
US11968832B2 (en) | 2024-04-23 |
CN111564450A (zh) | 2020-08-21 |
US20200035699A1 (en) | 2020-01-30 |
TW202008563A (zh) | 2020-02-16 |
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