SG11201701661UA - Method for processing semiconductor wafer, method for manufacturing bonded wafer, and method for manufacturing epitaxial wafer - Google Patents

Method for processing semiconductor wafer, method for manufacturing bonded wafer, and method for manufacturing epitaxial wafer

Info

Publication number
SG11201701661UA
SG11201701661UA SG11201701661UA SG11201701661UA SG11201701661UA SG 11201701661U A SG11201701661U A SG 11201701661UA SG 11201701661U A SG11201701661U A SG 11201701661UA SG 11201701661U A SG11201701661U A SG 11201701661UA SG 11201701661U A SG11201701661U A SG 11201701661UA
Authority
SG
Singapore
Prior art keywords
wafer
manufacturing
processing semiconductor
semiconductor wafer
bonded
Prior art date
Application number
SG11201701661UA
Other languages
English (en)
Inventor
Yuki Miyazawa
Takahiro Kida
Tomofumi Takano
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201701661UA publication Critical patent/SG11201701661UA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B21/00—Machines or devices using grinding or polishing belts; Accessories therefor
    • B24B21/04—Machines or devices using grinding or polishing belts; Accessories therefor for grinding plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/02—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent
    • B24B49/04—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent involving measurement of the workpiece at the place of grinding during grinding operation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
SG11201701661UA 2014-09-11 2015-08-19 Method for processing semiconductor wafer, method for manufacturing bonded wafer, and method for manufacturing epitaxial wafer SG11201701661UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014185325A JP6045542B2 (ja) 2014-09-11 2014-09-11 半導体ウェーハの加工方法、貼り合わせウェーハの製造方法、及びエピタキシャルウェーハの製造方法
PCT/JP2015/004130 WO2016038800A1 (fr) 2014-09-11 2015-08-19 Procédé de traitement de tranche de semi-conducteur, procédé de fabrication de tranche liée, et procédé de fabrication de plaquette épitaxiale

Publications (1)

Publication Number Publication Date
SG11201701661UA true SG11201701661UA (en) 2017-04-27

Family

ID=55458575

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201701661UA SG11201701661UA (en) 2014-09-11 2015-08-19 Method for processing semiconductor wafer, method for manufacturing bonded wafer, and method for manufacturing epitaxial wafer

Country Status (8)

Country Link
US (1) US9905411B2 (fr)
EP (1) EP3193357B1 (fr)
JP (1) JP6045542B2 (fr)
KR (1) KR102088279B1 (fr)
CN (1) CN106663623B (fr)
SG (1) SG11201701661UA (fr)
TW (1) TWI595548B (fr)
WO (1) WO2016038800A1 (fr)

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JP6614076B2 (ja) * 2016-09-07 2019-12-04 信越半導体株式会社 貼り合わせ用基板の表面欠陥の評価方法
DE102017210423A1 (de) * 2017-06-21 2018-12-27 Siltronic Ag Verfahren, Steuerungssystem und Anlage zum Bearbeiten einer Halbleiterscheibe sowie Halbleiterscheibe
JP6750592B2 (ja) * 2017-08-15 2020-09-02 信越半導体株式会社 シリコンウエーハのエッジ形状の評価方法および評価装置、シリコンウエーハ、ならびにその選別方法および製造方法
US10732128B2 (en) * 2017-10-26 2020-08-04 Camtek Ltd. Hierarchical wafer inspection
EP3567138B1 (fr) * 2018-05-11 2020-03-25 SiCrystal GmbH Substrat de carbure de silicium chanfreinée et procédé de chanfreinage
EP3567139B1 (fr) 2018-05-11 2021-04-07 SiCrystal GmbH Substrat de carbure de silicium chanfreinée et procédé de chanfreinage
KR102444720B1 (ko) * 2018-09-14 2022-09-16 가부시키가이샤 사무코 웨이퍼의 경면 모따기 방법, 웨이퍼의 제조 방법 및, 웨이퍼
JP7084845B2 (ja) * 2018-10-25 2022-06-15 株式会社ディスコ ウェーハの製造方法
CN111430223B (zh) * 2020-05-15 2023-06-23 中国科学院微电子研究所 一种预清洗装置
CN111451909B (zh) * 2020-05-18 2021-06-11 立铠精密科技(盐城)有限公司 一种计算机系统用集成板磨边加工系统
CN111761419B (zh) * 2020-06-11 2021-10-15 上海中欣晶圆半导体科技有限公司 用于修复晶圆边缘损伤的胶带研磨工艺

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JP4846915B2 (ja) * 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
US6722964B2 (en) * 2000-04-04 2004-04-20 Ebara Corporation Polishing apparatus and method
DE10142400B4 (de) * 2001-08-30 2009-09-03 Siltronic Ag Halbleiterscheibe mit verbesserter lokaler Ebenheit und Verfahren zu deren Herstellung
JP4162892B2 (ja) * 2002-01-11 2008-10-08 日鉱金属株式会社 半導体ウェハおよびその製造方法
JP4093793B2 (ja) * 2002-04-30 2008-06-04 信越半導体株式会社 半導体ウエーハの製造方法及びウエーハ
JP3534115B1 (ja) * 2003-04-02 2004-06-07 住友電気工業株式会社 エッジ研磨した窒化物半導体基板とエッジ研磨したＧａＮ自立基板及び窒化物半導体基板のエッジ加工方法
JP4748968B2 (ja) * 2004-10-27 2011-08-17 信越半導体株式会社 半導体ウエーハの製造方法
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JP2006237055A (ja) * 2005-02-22 2006-09-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法および半導体ウェーハの鏡面面取り方法
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JP5644401B2 (ja) 2010-11-15 2014-12-24 株式会社Sumco エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP6027346B2 (ja) 2012-06-12 2016-11-16 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハの製造方法
JP6312976B2 (ja) * 2012-06-12 2018-04-18 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハの製造方法
JP5988765B2 (ja) * 2012-08-13 2016-09-07 ダイトエレクトロン株式会社 ウェーハの面取り加工方法、ウェーハの面取り加工装置および砥石角度調整用治具
JP6244962B2 (ja) * 2014-02-17 2017-12-13 株式会社Sumco 半導体ウェーハの製造方法

Also Published As

Publication number Publication date
CN106663623B (zh) 2019-06-14
EP3193357A1 (fr) 2017-07-19
TW201611112A (zh) 2016-03-16
EP3193357A4 (fr) 2018-08-01
JP6045542B2 (ja) 2016-12-14
KR20170051442A (ko) 2017-05-11
WO2016038800A1 (fr) 2016-03-17
US20170301533A1 (en) 2017-10-19
TWI595548B (zh) 2017-08-11
EP3193357B1 (fr) 2019-05-01
CN106663623A (zh) 2017-05-10
JP2016058623A (ja) 2016-04-21
KR102088279B1 (ko) 2020-03-12
US9905411B2 (en) 2018-02-27

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