SG11201505894RA - Sealing sheet for semiconductor element, semiconductor device, and semiconductor device production method - Google Patents
Sealing sheet for semiconductor element, semiconductor device, and semiconductor device production methodInfo
- Publication number
- SG11201505894RA SG11201505894RA SG11201505894RA SG11201505894RA SG11201505894RA SG 11201505894R A SG11201505894R A SG 11201505894RA SG 11201505894R A SG11201505894R A SG 11201505894RA SG 11201505894R A SG11201505894R A SG 11201505894RA SG 11201505894R A SG11201505894R A SG 11201505894RA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- production method
- semiconductor
- sealing sheet
- semiconductor element
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000007789 sealing Methods 0.000 title 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
- B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
- B32B3/30—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/18—Layered products comprising a layer of synthetic resin characterised by the use of special additives
- B32B27/20—Layered products comprising a layer of synthetic resin characterised by the use of special additives using fillers, pigments, thixotroping agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2264/00—Composition or properties of particles which form a particulate layer or are present as additives
- B32B2264/10—Inorganic particles
- B32B2264/107—Ceramic
- B32B2264/108—Carbon, e.g. graphite particles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/50—Properties of the layers or laminate having particular mechanical properties
- B32B2307/538—Roughness
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/70—Other properties
- B32B2307/748—Releasability
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2581/00—Seals; Sealing equipment; Gaskets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013027942 | 2013-02-15 | ||
JP2014022331A JP2014179593A (ja) | 2013-02-15 | 2014-02-07 | 半導体素子用封止シート、半導体装置及び半導体装置の製造方法 |
PCT/JP2014/053321 WO2014126150A1 (ja) | 2013-02-15 | 2014-02-13 | 半導体素子用封止シート、半導体装置及び半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201505894RA true SG11201505894RA (en) | 2015-09-29 |
Family
ID=51354149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201505894RA SG11201505894RA (en) | 2013-02-15 | 2014-02-13 | Sealing sheet for semiconductor element, semiconductor device, and semiconductor device production method |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP2014179593A (ko) |
KR (1) | KR20150117653A (ko) |
SG (1) | SG11201505894RA (ko) |
TW (1) | TWI618200B (ko) |
WO (1) | WO2014126150A1 (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6302801B2 (ja) | 2014-09-03 | 2018-03-28 | 日東電工株式会社 | 封止用シート |
US9337064B2 (en) * | 2014-09-15 | 2016-05-10 | Micron Technology, Inc. | Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems |
JP5976073B2 (ja) * | 2014-11-07 | 2016-08-23 | 日東電工株式会社 | 半導体装置の製造方法 |
JP6379051B2 (ja) * | 2015-01-23 | 2018-08-22 | 日東電工株式会社 | 中空型電子デバイス封止用シート |
JP6443155B2 (ja) * | 2015-03-19 | 2018-12-26 | 東レ株式会社 | 離型用二軸配向ポリエステルフィルム |
JPWO2017038110A1 (ja) * | 2015-08-28 | 2018-06-07 | 日立化成株式会社 | 半導体装置及びその製造方法 |
US20210276316A1 (en) * | 2016-09-30 | 2021-09-09 | Unitika Ltd. | Polyester film |
JP7173740B2 (ja) * | 2018-03-08 | 2022-11-16 | 日東電工株式会社 | 封止用シート |
JP6795673B2 (ja) * | 2019-12-19 | 2020-12-02 | 日東電工株式会社 | 電子デバイス封止用シート、及び、電子デバイスパッケージの製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3188537B2 (ja) * | 1992-10-30 | 2001-07-16 | トーワ株式会社 | 電子部品の樹脂封止成形用金型と成形方法及び樹脂成形品 |
JPH0853604A (ja) * | 1994-08-10 | 1996-02-27 | Sumitomo Bakelite Co Ltd | 半導体封止用樹脂組成物 |
JP3958864B2 (ja) * | 1998-05-21 | 2007-08-15 | 浜松ホトニクス株式会社 | 透明樹脂封止光半導体装置 |
JP2002110722A (ja) * | 2000-10-03 | 2002-04-12 | Nitto Denko Corp | 半導体チップの樹脂封止方法及び半導体チップ樹脂封止用離型フィルム |
JP2002170921A (ja) * | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4682796B2 (ja) * | 2005-04-19 | 2011-05-11 | 日立化成工業株式会社 | 封止用シート |
JP5110440B2 (ja) * | 2006-08-18 | 2012-12-26 | 旭硝子株式会社 | 半導体樹脂モールド用の離型フィルム |
JP5401819B2 (ja) * | 2007-04-18 | 2014-01-29 | 日立化成株式会社 | 封止用フィルム及びそれを用いた半導体装置 |
JP2011014606A (ja) * | 2009-06-30 | 2011-01-20 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP5827864B2 (ja) * | 2011-06-14 | 2015-12-02 | 日東電工株式会社 | 封止用シートおよび光半導体素子装置 |
JP5634467B2 (ja) * | 2012-09-21 | 2014-12-03 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
-
2014
- 2014-02-07 JP JP2014022331A patent/JP2014179593A/ja active Pending
- 2014-02-13 SG SG11201505894RA patent/SG11201505894RA/en unknown
- 2014-02-13 WO PCT/JP2014/053321 patent/WO2014126150A1/ja active Application Filing
- 2014-02-13 KR KR1020157020563A patent/KR20150117653A/ko not_active Application Discontinuation
- 2014-02-14 TW TW103104996A patent/TWI618200B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP2014179593A (ja) | 2014-09-25 |
TW201442164A (zh) | 2014-11-01 |
KR20150117653A (ko) | 2015-10-20 |
WO2014126150A1 (ja) | 2014-08-21 |
TWI618200B (zh) | 2018-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
HK1214408A1 (zh) | 半導體裝置及其製造方法 | |
EP2930741A4 (en) | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT | |
HK1205357A1 (en) | Semiconductor device and method for manufacturing the same | |
EP2833405A4 (en) | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF | |
SG10201406149PA (en) | Semiconductor Device And Method For Manufacturing The Same | |
EP3037776A4 (en) | WORKING METHOD FOR PRODUCING A SUBSTRATE, METHOD FOR DETERMINING SUBSTRATE IMAGING CONDITIONS AND WORKING DEVICE FOR PRODUCING A SUBSTRATE | |
EP2960925A4 (en) | COMPOSITE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | |
EP2985614A4 (en) | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT | |
HK1219174A1 (zh) | 標記形成方法、標記檢測方法及器件製造方法 | |
SG11201505894RA (en) | Sealing sheet for semiconductor element, semiconductor device, and semiconductor device production method | |
EP2944248A4 (en) | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT, SEMICONDUCTOR COMPONENT AND ENDOSCOPE | |
HK1219347A1 (zh) | 半導體裝置及其製造方法 | |
HK1210869A1 (en) | Semiconductor device and method for manufacturing the same | |
EP2955748A4 (en) | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF | |
EP2980176A4 (en) | PRODUCTION METHOD FOR LAMINATED FILM, LAMINATED FILM, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE USING THE SAME | |
SG11201600747VA (en) | Sheet for sealing and method for manufacturing semiconductor device using said sheet for sealing | |
SG11201508291QA (en) | Semiconductor device and method for manufacturing semiconductor device | |
SG11201604064RA (en) | Sealing thermosetting-resin sheet and hollow-package manufacturing method | |
EP2949308A4 (en) | MASSAGE DEVICE, AND PRODUCTION METHOD, AND PRODUCTION DEVICE THEREFOR | |
EP3073158A4 (en) | METHOD FOR PRODUCING SEALING DEVICE | |
TWI562316B (en) | Semiconductor device and method for fabricating the same | |
SG11201701445PA (en) | Sealing sheet, sealing sheet with separator, semiconductor device, and production method for semiconductor device | |
EP2919273A4 (en) | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT | |
SG11201605151TA (en) | Sealing sheet provided with double-sided separator, and method for manufacturing semiconductor device | |
SG11201510008UA (en) | Semiconductor device and manufacturing method therefor |