SG10201908410QA - Semiconductor device including gate pattern having pad region - Google Patents
Semiconductor device including gate pattern having pad regionInfo
- Publication number
- SG10201908410QA SG10201908410QA SG10201908410QA SG10201908410QA SG10201908410QA SG 10201908410Q A SG10201908410Q A SG 10201908410QA SG 10201908410Q A SG10201908410Q A SG 10201908410QA SG 10201908410Q A SG10201908410Q A SG 10201908410QA SG 10201908410Q A SG10201908410Q A SG 10201908410QA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- device including
- gate pattern
- pad region
- including gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020180109777A KR102507288B1 (ko) | 2018-09-13 | 2018-09-13 | 패드 영역을 갖는 게이트 패턴을 포함하는 반도체 소자 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201908410QA true SG10201908410QA (en) | 2020-04-29 |
Family
ID=69772389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201908410QA SG10201908410QA (en) | 2018-09-13 | 2019-09-11 | Semiconductor device including gate pattern having pad region |
Country Status (4)
Country | Link |
---|---|
US (1) | US10950544B2 (zh) |
KR (2) | KR102507288B1 (zh) |
CN (1) | CN110896101A (zh) |
SG (1) | SG10201908410QA (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102633107B1 (ko) * | 2018-09-21 | 2024-02-05 | 에스케이하이닉스 주식회사 | 수직형 메모리 장치 및 그 제조 방법 |
KR20200115769A (ko) * | 2019-03-25 | 2020-10-08 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
KR20220037633A (ko) * | 2020-09-18 | 2022-03-25 | 에스케이하이닉스 주식회사 | 메모리 장치 및 그 제조방법 |
US11610842B2 (en) * | 2020-12-02 | 2023-03-21 | Macronix International Co., Ltd. | Memory device and method of manufacturing the same |
KR20220114856A (ko) * | 2021-02-09 | 2022-08-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 제조방법 |
US20230262976A1 (en) * | 2022-02-17 | 2023-08-17 | Micron Technology, Inc | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100459724B1 (ko) | 2002-09-11 | 2004-12-03 | 삼성전자주식회사 | 저온 원자층증착에 의한 질화막을 식각저지층으로이용하는 반도체 소자 및 그 제조방법 |
KR101585616B1 (ko) * | 2009-12-16 | 2016-01-15 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
WO2014034748A1 (ja) | 2012-08-29 | 2014-03-06 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
KR20140089793A (ko) | 2013-01-07 | 2014-07-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
JP2015041674A (ja) | 2013-08-21 | 2015-03-02 | マイクロン テクノロジー, インク. | 半導体装置およびその製造方法 |
KR20150073251A (ko) * | 2013-12-20 | 2015-07-01 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
US9929279B2 (en) | 2014-02-05 | 2018-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR102094470B1 (ko) * | 2014-04-08 | 2020-03-27 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR102282138B1 (ko) * | 2014-12-09 | 2021-07-27 | 삼성전자주식회사 | 반도체 소자 |
US9484357B2 (en) | 2014-12-16 | 2016-11-01 | Sandisk Technologies Llc | Selective blocking dielectric formation in a three-dimensional memory structure |
US9431235B1 (en) | 2015-04-24 | 2016-08-30 | International Business Machines Corporation | Multilayer dielectric structures with graded composition for nano-scale semiconductor devices |
US10312138B2 (en) * | 2016-08-16 | 2019-06-04 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US10229929B2 (en) * | 2016-12-09 | 2019-03-12 | Samsung Electronics Co., Ltd. | Semiconductor memory devices including protrusion pads |
-
2018
- 2018-09-13 KR KR1020180109777A patent/KR102507288B1/ko active IP Right Grant
-
2019
- 2019-06-18 US US16/445,021 patent/US10950544B2/en active Active
- 2019-09-11 SG SG10201908410QA patent/SG10201908410QA/en unknown
- 2019-09-12 CN CN201910862596.9A patent/CN110896101A/zh active Pending
-
2023
- 2023-03-02 KR KR1020230027817A patent/KR20230035553A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US20200091071A1 (en) | 2020-03-19 |
US10950544B2 (en) | 2021-03-16 |
KR20200031205A (ko) | 2020-03-24 |
CN110896101A (zh) | 2020-03-20 |
KR20230035553A (ko) | 2023-03-14 |
KR102507288B1 (ko) | 2023-03-08 |
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