SG10201907872RA - Semiconductor package including test pad - Google Patents
Semiconductor package including test padInfo
- Publication number
- SG10201907872RA SG10201907872RA SG10201907872RA SG10201907872RA SG10201907872RA SG 10201907872R A SG10201907872R A SG 10201907872RA SG 10201907872R A SG10201907872R A SG 10201907872RA SG 10201907872R A SG10201907872R A SG 10201907872RA SG 10201907872R A SG10201907872R A SG 10201907872RA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor package
- test pad
- package including
- including test
- pad
- Prior art date
Links
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/802—Applying energy for connecting
- H01L2224/80201—Compression bonding
- H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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- H01L2224/92—Specific sequence of method steps
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- H01L2224/92—Specific sequence of method steps
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- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
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KR1020180129137A KR102674029B1 (en) | 2018-10-26 | 2018-10-26 | Semiconductor package including test pad |
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EP (1) | EP3647800A1 (en) |
KR (1) | KR102674029B1 (en) |
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CN109285825B (en) * | 2017-07-21 | 2021-02-05 | 联华电子股份有限公司 | Chip stacking structure and manufacturing method of tube core stacking structure |
WO2020044871A1 (en) * | 2018-08-31 | 2020-03-05 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device, semiconductor testing apparatus, and testing method for semiconductor device |
KR102596758B1 (en) * | 2018-10-24 | 2023-11-03 | 삼성전자주식회사 | Semiconductor package |
US11562982B2 (en) * | 2019-04-29 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages and methods of forming the same |
US11476201B2 (en) * | 2019-09-27 | 2022-10-18 | Taiwan Semiconductor Manufacturing Company. Ltd. | Package-on-package device |
DE102020108481B4 (en) | 2019-09-27 | 2023-07-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die package and manufacturing process |
CN111710659B (en) * | 2020-07-01 | 2021-10-22 | 无锡中微亿芯有限公司 | Silicon connection layer test circuit for testing by using test bare chip |
FR3116268B1 (en) * | 2020-11-16 | 2023-10-20 | Commissariat Energie Atomique | Electronic circuit for hybrid molecular bonding |
JP2022191901A (en) * | 2021-06-16 | 2022-12-28 | キオクシア株式会社 | Semiconductor device and method for manufacturing the same |
US11942391B2 (en) | 2021-11-30 | 2024-03-26 | Qorvo Us, Inc. | System in package with flip chip die over multi-layer heatsink stanchion |
CN117198988A (en) * | 2022-06-01 | 2023-12-08 | 长鑫存储技术有限公司 | Packaging structure, packaging method and semiconductor device |
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US7598523B2 (en) * | 2007-03-19 | 2009-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structures for stacking dies having through-silicon vias |
KR101478247B1 (en) | 2008-03-12 | 2014-12-31 | 삼성전자주식회사 | semiconductor package and multi-chip package using the same |
JP2008182264A (en) | 2008-03-18 | 2008-08-07 | Matsushita Electric Ind Co Ltd | Semiconductor device, manufacturing and inspection methods therefor |
US7973310B2 (en) | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
KR101535223B1 (en) | 2008-08-18 | 2015-07-09 | 삼성전자주식회사 | Tape wiring substrate, chip on film package and device assembly including the same |
US20110241185A1 (en) * | 2010-04-05 | 2011-10-06 | International Business Machines Corporation | Signal shielding through-substrate vias for 3d integration |
KR101142339B1 (en) | 2010-06-17 | 2012-05-17 | 에스케이하이닉스 주식회사 | Semiconductor chip |
JP5399982B2 (en) | 2010-06-17 | 2014-01-29 | 浜松ホトニクス株式会社 | Inspection method of semiconductor integrated circuit device and semiconductor integrated circuit device |
US8421073B2 (en) * | 2010-10-26 | 2013-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC) |
US8664540B2 (en) * | 2011-05-27 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer testing using dummy connections |
KR20130022829A (en) * | 2011-08-26 | 2013-03-07 | 삼성전자주식회사 | Method for detecting defect of multi-chip packaging device and method for manufacturing the multi-chip packaging device using the same |
KR20130044048A (en) | 2011-10-21 | 2013-05-02 | 에스케이하이닉스 주식회사 | Semiconductor wafer and method for fabricating stack package using the same |
JP2013131533A (en) | 2011-12-20 | 2013-07-04 | Elpida Memory Inc | Semiconductor device |
TWI483378B (en) | 2013-01-04 | 2015-05-01 | Tsai Yu Huang | Three dimensional stacked structure for chips |
JP2014187185A (en) * | 2013-03-22 | 2014-10-02 | Renesas Electronics Corp | Semiconductor device manufacturing method |
JP2015046569A (en) * | 2013-07-31 | 2015-03-12 | マイクロン テクノロジー, インク. | Semiconductor device manufacturing method |
KR102258739B1 (en) | 2014-03-26 | 2021-06-02 | 삼성전자주식회사 | Semiconductor devices having hybrid stacking structures and methods for fabricating the same |
KR102360381B1 (en) | 2014-12-01 | 2022-02-11 | 삼성전자주식회사 | Semiconductor devices having stacking structures and methods for fabricating the same |
US10163859B2 (en) | 2015-10-21 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method for chip package |
US11393779B2 (en) * | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
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KR20200047930A (en) | 2020-05-08 |
TWI772698B (en) | 2022-08-01 |
US20200135594A1 (en) | 2020-04-30 |
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