CN111710659B - Silicon connection layer test circuit for testing by using test bare chip - Google Patents
Silicon connection layer test circuit for testing by using test bare chip Download PDFInfo
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- CN111710659B CN111710659B CN202010620243.0A CN202010620243A CN111710659B CN 111710659 B CN111710659 B CN 111710659B CN 202010620243 A CN202010620243 A CN 202010620243A CN 111710659 B CN111710659 B CN 111710659B
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- H01—ELECTRIC ELEMENTS
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The utility model provides a silicon connecting layer test circuit who utilizes test bare chip to test relates to the semiconductor technology field, lay JTAG control logic and boundary scan test chain in test bare chip inside in order to form test circuit, test bare chip and silicon connecting layer surface lay the tie point of the same mode of arranging, can realize the butt joint between the tie point when making test bare chip arrange carrier on with silicon connecting layer surface laminating, thereby can utilize the test circuit inside the test bare chip to accomplish the test excitation transmission and the test result of signal path structure in the silicon connecting layer and catch, can easily realize the test to silicon connecting layer in order to carry out the rapid screening to silicon connecting layer before the assembly, guarantee that the later stage can adopt the normal silicon connecting layer of function and bare chip equipment to form normal many bare chip silicon and pile up interconnect structure, in order to guarantee the production yield.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon connection layer test circuit for testing by using a test bare chip.
Background
An FPGA (Field Programmable Gate Array) is a Programmable logic device of hardware, and is widely applied to prototype verification in integrated circuit design besides the fields of mobile communication, data center, etc., so as to effectively verify the correctness of circuit functions and accelerate the circuit design speed. The prototype verification needs to realize circuit design by using programmable logic resources inside the FPGA, the demand for the number of the programmable logic resources of the FPGA is continuously increased along with the continuous increase of the scale of the integrated circuit and the realization of complex functions, the number of the programmable resources of the FPGA becomes a larger bottleneck due to the continuous increase of the subsequent technical development and demand, and a larger challenge is provided for the development of the industry. The increase in the FPGA scale represents an increasing chip area, which leads to an increase in chip processing difficulty and a decrease in chip production yield.
At present, some patents propose a method for designing chip interconnection through a silicon stack interconnection technology (SSI), in which a silicon connection layer is required to be used to realize signal interconnection of a bare chip, but in actual production, a situation that the whole FPGA is affected due to abnormal function of the silicon connection layer is often found after assembly, and the production yield is difficult to guarantee.
Disclosure of Invention
The present invention provides a silicon connection layer test circuit for testing by using a test bare chip, which includes a test bare chip and a silicon connection layer to be tested;
the surface of the silicon connecting layer is preset with a plurality of connecting points, wherein the connecting points comprise a silicon connecting layer input connecting point and a silicon connecting layer output connecting point; a signal path structure communicated between the silicon connection layer input connection point and the corresponding silicon connection layer output connection point is distributed in the silicon connection layer;
a plurality of bare chip input connection points and a plurality of bare chip output connection points are preset on the surface of the test bare chip, the bare chip input connection points and the bare chip output connection points are arranged on the surface of the test bare chip in an array structure, and the relative arrangement structure between the connection points on the surface of the test bare chip is matched with the relative arrangement structure between the connection points on the silicon connection layer;
the inside of the test bare chip is also provided with JTAG control logic and a plurality of boundary scanning cell structures, each boundary scanning cell structure comprises a data input end, a data output end, a scanning input end and a scanning output end, each boundary scanning cell structure corresponds to one connecting point on the surface of the test bare chip respectively, the data input end of the boundary scanning cell structure corresponding to the input connecting point of the bare chip is connected with the input connecting point of the bare chip, and the data output end of the boundary scanning cell structure corresponding to the output connecting point of the bare chip is connected with the output connecting point of the bare chip; each boundary scanning cell structure is connected with the adjacent boundary scanning cell structure through a scanning input end and a scanning output end respectively, so that each boundary scanning cell structure is sequentially connected in series to form a boundary scanning test chain, and two ends of the formed boundary scanning test chain are connected to the JTAG control logic;
the test bare chip is arranged on the carrier, the connection points on the surface of the test bare chip are respectively attached to the connection points on the surface of the silicon connection layer, the input connection points of the bare chip are respectively butted with the output connection points of the silicon connection layer, and the output connection points of the bare chip are respectively butted with the input connection points of the silicon connection layer; and the JTAG control logic inside the test bare chip carries out test excitation transmission and test result capture on the connection point in the silicon connection layer through the boundary scan test chain so as to realize the test on the signal path structure inside the silicon connection layer.
The method comprises the following steps that a JTAG control logic in a test die transmits test excitation to boundary scan cell structures connected with output connection points of each die through a boundary scan test chain so as to transmit the test excitation to corresponding silicon connection layer input connection points, the test excitation is transmitted to corresponding silicon connection layer output connection points through a signal path structure between internal connection points of the silicon connection layers and is transmitted to the boundary scan cell structures connected with the corresponding die input connection points to form a test result, and the test result is transmitted to the JTAG control logic through the boundary scan test chain.
The test circuit of the silicon connection layer comprises a plurality of test bare chips, wherein each test bare chip is arranged on the carrier, the connection points on the surface of the test bare chip are respectively attached to the corresponding connection points on the surface of the silicon connection layer, and all the test bare chips cover all the connection points on the surface of the silicon connection layer;
the JTAG control logic in any first test die transmits test excitation to the boundary scan cell structure connected with each die output connection point through the boundary scan test chain so as to transmit the test excitation to the corresponding silicon connection layer input connection point, the test excitation is transmitted to the corresponding silicon connection layer output connection point through a signal path structure between the silicon connection layer internal connection points and is transmitted to the boundary scan cell structure connected with the die input connection point in the corresponding second test die to form a test result, the test result is transmitted to the JTAG control logic in the second test die through the boundary scan test chain in the second test die, and a plurality of test dies jointly complete the test on the silicon connection layer.
The technical scheme is that each test bare chip is also provided with a test interface connected with the internal JTAG control logic, the test interface at least comprises a data input end and a data output end, and the JTAG control logic inside each test bare chip is sequentially connected in series through the data input end and the data output end.
The test method comprises the following steps that a stimulus generating circuit and a test response analyzing circuit which are connected to a boundary scanning test chain are further arranged in a test bare chip, test stimulus is generated by JTAG control logic according to test vectors generated by the stimulus generating circuit, and the test results are acquired by the JTAG control logic and then transmitted to the test response analyzing circuit to compare expected test results corresponding to the test vectors and actually acquired test results to finish testing the silicon connection layer.
The test bare chip is also provided with a test interface connected with an internal JTAG control logic, the test bare chip is connected with an external ATE tester through the test interface, the external ATE tester generates test excitation according to the test vector and outputs the test excitation to the JTAG control logic through the test interface, the JTAG control logic formats and outputs the test result to the external ATE tester, and the external ATE tester compares the expected test result corresponding to the test vector with the actually obtained test result to finish testing the silicon connection layer.
The further technical scheme is that each boundary scan cell structure inside the test die comprises a first multiplexer, a second multiplexer, a capture register and an update register, wherein a data input end of the boundary scan cell structure is connected with one input end of the first multiplexer and one input end of the second multiplexer, a scan input end of the boundary scan cell structure is connected with the other input end of the first multiplexer, an output end of the first multiplexer is connected with an input end of the capture register, an output end of the capture register is connected with an input end of the update register and a scan output end of the boundary scan cell structure, an output end of the update register is connected with the other input end of the second multiplexer, and an output end of the second multiplexer is connected with a data output end of the boundary scan cell structure.
The beneficial technical effects of the invention are as follows:
the application provides a silicon connection layer test circuit for testing by using a test bare chip, JTAG control logic and a boundary scan test chain are arranged inside the test bare chip to form a test circuit, the test bare chip and the surface of a silicon connection layer are provided with connection points in the same arrangement mode, so that the test bare chip can realize the butt joint between the connection points when being arranged on a carrier and attached to the surface of the silicon connection layer, thereby completing the test excitation transmission and test result capture of a signal path structure in the silicon connection layer by using the test circuit inside the test bare chip, easily realizing the test of the silicon connection layer to rapidly screen the silicon connection layer before assembly, ensuring that a normal multi-bare chip silicon stacking interconnection structure can be formed by assembling the silicon connection layer with normal functions and the bare chip in the later stage, and ensuring the production yield. And the silicon connection layer test circuit can support an external ATE test machine to realize the mass production test of the silicon connection layer.
Drawings
Fig. 1 is a schematic structural diagram of a silicon connection layer test circuit according to the present application.
Fig. 2 is a schematic diagram of the interface of test die surface connection points and silicon connection layer surface connection points.
Fig. 3 is a schematic circuit diagram of a test die.
FIG. 4 is a circuit diagram of the structure of each boundary-scan cell within the test die.
FIG. 5 is a schematic diagram of a cascade of a plurality of test dies in the silicon interconnect layer test circuit.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The present application provides a silicon-bonded layer test circuit for testing using a test die, the silicon-bonded layer test circuit includes a silicon-bonded layer 1 to be tested and a test die 2 for testing the silicon-bonded layer 1, please refer to fig. 1, the silicon-bonded layer 1 is mainly used for signal interconnection between dies inside a multi-die device, and the test circuit is used for testing the silicon-bonded layer 1 before assembly.
Referring to fig. 2, a plurality of silicon connection layer input connection points 11 and a plurality of silicon connection layer output connection points 12 are preset on the surface of the silicon connection layer 1, and these connection points are used for corresponding connection with connection points on the surface of the bare chip during assembly, and the silicon connection layer input connection points 11 and the silicon connection layer output connection points 12 are arranged according to a preset structure.
In order to improve the structural universality of the silicon connection layer, the silicon connection layer input connection points 11 and the silicon connection layer output connection points 12 are generally configured to be arranged on the surface of the silicon connection layer 1 in an array structure, that is, in the present application, a plurality of input connection point rows and a plurality of output connection point rows are arranged on the silicon connection layer 1, each input connection point row includes a plurality of silicon connection layer input connection points 11 arranged in a row, each output connection point row includes a plurality of silicon connection layer output connection points 12 arranged in a row, the input connection point rows and the output connection point rows are alternately arranged at intervals, and the intervals between any two adjacent rows are equal, as shown in fig. 1, the intervals are all L. The spacing between two adjacent silicon interconnect layer input interconnects 11 in each input interconnect column is generally equal to L1, and the spacing between two adjacent silicon interconnect layer output interconnects 12 in each output interconnect column is generally equal to L2. L1 and L2 may be equal or different, but are usually equal in actual operation. L1, L2 and L may be equal or different, but are usually arranged to be equal in practical operation, so that the distance between any two adjacent connection points on the surface of the silicon connection layer 1 is equal, and a regular row-column structure with equal distance is formed.
No matter what arrangement mode is adopted by the connection points on the surface of the silicon connection layer 1, a signal path structure communicated between the input connection points of the silicon connection layer and the corresponding output connection points of the silicon connection layer is arranged in the silicon connection layer 1, please refer to the connection schematic diagram between the connection points shown in fig. 1. The signal path structure can have a plurality of conditions: (1) the silicon connecting layer input connecting point is directly connected with the corresponding silicon connecting layer output connecting point through a metal connecting line. (2) The silicon connecting layer input connecting points are connected with the corresponding silicon connecting layer output connecting points through metal connecting lines, and passive devices are distributed on the metal connecting lines. (3) The silicon connecting layer input connecting points are connected with the corresponding silicon connecting layer output connecting points through metal connecting lines, and active devices are distributed on the metal connecting lines.
The surface of the test bare chip 2 is also preset with a plurality of bare chip input connection points 21 and a plurality of bare chip output connection points 22, the bare chip input connection points 21 and the bare chip output connection points 22 are arranged on the surface of the test bare chip in an array structure, the relative arrangement structure formed between the connection points is matched with the relative arrangement structure of the connection points on the silicon connection layer 1, the bare chip input connection points 21 correspond to the silicon connection layer input connection points 11, and the bare chip output connection points 22 correspond to the silicon connection layer output connection points 12. In the structure of the application, the connection points on the surface of the test bare chip are also arranged in a row, that is, a plurality of bare chip input connection point rows and a plurality of bare chip output connection point rows are arranged on the surface of the test bare chip, each bare chip input connection point row comprises a plurality of bare chip input connection points 21 arranged in a row, each bare chip output connection point row comprises a plurality of bare chip output connection points 22 arranged in a row, the input connection point rows and the output connection point rows are alternately arranged at intervals, the intervals between any two adjacent rows are equal, and the intervals are equal to the intervals between two adjacent rows on the silicon connection layer 1 and are also L. The spacing between two adjacent die input connection points 21 in each die input connection point row is generally equal and equal to the spacing between two adjacent silicon connection layer output connection points 12 in the output connection point row on silicon connection layer 1, i.e. L2. The spacing between two adjacent die output connection points 22 in each die output connection point row is generally equal and equal to the spacing between two adjacent silicon connection layer input connection points 11 in the input connection point row on silicon connection layer 1, i.e., L1.
Referring to fig. 3, the test die 2 is further disposed therein with JTAG control logic and a plurality of boundary SCAN CELL structures CELL, each of which includes a DATA input terminal DATA _ IN, a DATA output terminal DATA _ OUT, a SCAN input terminal SCAN _ IN and a SCAN output terminal SCAN _ OUT, and each of the boundary SCAN CELL structures corresponds to a connection point on the surface of the test die 2: the DATA input terminal DATA _ IN of the boundary-scan cell structure corresponding to the die input connection point 21 is connected to the die input connection point 21 and the DATA output terminal DATA _ OUT is floating, and the DATA output terminal DATA _ OUT of the boundary-scan cell structure corresponding to the die output connection point 22 is connected to the die output connection point 22 and the DATA input terminal DATA _ IN is floating. Each boundary SCAN cell structure is connected with the adjacent boundary SCAN cell structure through a SCAN input end SCAN _ IN and a SCAN output end SCAN _ OUT respectively, so that the boundary SCAN cell structures are sequentially connected IN series to form a boundary SCAN test chain, and two ends of the formed boundary SCAN test chain are connected to JTAG control logic.
Referring to fig. 4, each CELL structure includes a first multiplexer MUX1, a second multiplexer MUX2, a capture register S1, and an update register S2, wherein the capture register S1 and the update register S2 are implemented by D flip-flops. The DATA input terminal DATA _ IN of the boundary-SCAN CELL structure is connected to an input terminal of the first multiplexer MUX1 and an input terminal of the second multiplexer MUX2, the SCAN input terminal SCAN _ IN of the boundary-SCAN CELL structure CELL is connected to another input terminal of the first multiplexer MUX1, the output terminal of the first multiplexer MUX1 is connected to an input terminal of the capture register S1, the output terminal of the capture register S1 is connected to an input terminal of the update register S2 and to a SCAN output terminal SCAN _ OUT of the boundary-SCAN CELL structure, the output terminal of the update register S2 is connected to another input terminal of the second multiplexer MUX2, and the output terminal of the second multiplexer MUX2 is connected to the DATA output terminal DATA _ OUT of the boundary-SCAN CELL structure.
As shown in fig. 1, when testing the silicon connection layer 1 by using the test circuit, the test die 2 is disposed on the carrier 3 and is butted with the silicon connection layer 1, and the matching connection point arrangement structures on the silicon connection layer 1 and the test die 2 make the connection points on the test die 2 respectively fit with the connection points on the silicon connection layer 1, and the respective die input connection points 21 on the test die 2 are respectively butted with the respective silicon connection layer output connection points 12, and the respective die output connection points 22 on the test die are respectively butted with the respective silicon connection layer input connection points 11, as shown in fig. 1.
After the bonding and docking are completed, the JTAG control logic inside the test die 2 may perform test excitation transmission and test result capture on the signal path structure between the connection points in the silicon connection layer 1 through the internal boundary scan test chain to realize the test on the silicon connection layer 1. Specifically, the method comprises the following steps: the JTAG control logic within the test die 2 transmits test stimuli via the boundary scan test chain to the boundary scan cell structures connected to the respective die output connection points 22 to the respective interfacing silicon connection layer input connection points 11 via the die output connection points 22, the test stimuli are transmitted via the signal path structures between the internal connection points of the silicon connection layers to the respective silicon connection layer output connection points 12 and to the respective die input connection points 21, and the boundary scan cell structures connected to the die input connection points 21 form test results, which are transmitted via the boundary scan test chain to the JTAG control logic, therefore, test excitation transmission and test result capture are completed, the test of the signal path structure in the silicon connecting layer is realized, and the silicon connecting layer passing the test can be used in a multi-die device to be assembled with a die to form a multi-die silicon stacked interconnection structure. Each test stimulus corresponds to an expected test result, and the expected test result is compared with the actually captured test result to obtain final test data.
Since the silicon connection layer 1 is usually large, a single test die 2 is not used in the silicon connection layer test circuit, but a plurality of test dies are included, the layout structure of the connection points on the surface of each test die is the same, and the structure is adopted internally, but the area and the shape of each test die can be different, for example, fig. 2 takes the shape and the size of each test die as the example. All the test bare chips 2 are arranged on the carrier 3, and the connection points on the surfaces of all the test bare chips 2 are respectively attached to the corresponding connection points on the surface of the silicon connection layer 1 and cover all the connection points on the surface of the silicon connection layer, so that the full-coverage test of the silicon connection layer is completed. The way of jointly testing the silicon connection layer 1 by the plurality of test dies 2 is similar to the test process of a single test die, specifically: the JTAG control logic in any first test die transmits test stimuli via boundary scan test chains to boundary scan cell structures connected to respective die output connection points 22 to respective silicon connection layer input connection points 11, the test stimuli are transmitted via signal path structures between internal connection points of the silicon connection layer 1 to respective silicon connection layer output connection points 12 and to respective boundary scan cell structures connected to die input connection points 21 in a second test die to form test results, the test results are transmitted via boundary scan test chains in the second test die to JTAG control logic in the second test die, and a plurality of test dies jointly complete testing the silicon connection layer.
When a plurality of test dies 2 are used to test a silicon connection layer together, each test die 2 is further provided with a test interface for connecting internal JTAG control logic, as shown in fig. 5, the test interface at least includes a data input terminal TDI and a data output terminal TDO, the actual test interface further includes a clock input terminal TCK and a mode selection segment TMS, the JTAG control logic inside each test die is sequentially connected in series through the data input terminal and the data output terminal, the TCK and the TMS of each test die are respectively connected correspondingly, that is, the boundary scan test chains inside the plurality of test dies are connected in series to form a larger boundary scan test chain, and fig. 5 exemplifies a case that four test dies are included in fig. 2.
When the JTAG control logic carries out test excitation transmission and test result capture, two implementation modes are provided:
1. the test die has built-in stimulus generation circuitry (TPG) and test response analysis circuitry (ORA), both connected to a boundary scan test chain inside the test die. Test vectors are generated by the TPG inside the test die, and the JTAG control logic generates test stimulus according to the test vectors generated by the TPG and transmits the test stimulus. And after capturing the test result, transmitting the test result to an ORA inside the test bare chip, and directly comparing the expected test result corresponding to the test vector and the actually obtained test result by the internal ORA to finish the test of the silicon connection layer.
2. The test die is also provided with a test interface to connect the internal JTAG control logic, with the specific terminals of the test interface being as described above. The test bare chip is connected with an external ATE tester through the test interface, the external ATE tester generates test excitation according to the test vector and injects the test excitation into the test bare chip through the test interface, and the JTAG control logic receives the externally injected test excitation and transmits the test excitation. And after capturing the test result, the JTAG control logic formats the test result and outputs the test result to an external ATE tester, and the external ATE tester compares the expected test result corresponding to the test vector with the actually obtained test result to finish the test of the silicon connection layer. The external ATE machine is very suitable for mass production test.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (7)
1. A silicon connection layer test circuit for testing by using a test bare chip is characterized in that the silicon connection layer test circuit comprises the test bare chip and a silicon connection layer to be tested;
the surface of the silicon connecting layer is preset with a plurality of connecting points, wherein the connecting points comprise a silicon connecting layer input connecting point and a silicon connecting layer output connecting point, and the silicon connecting layer input connecting point and the silicon connecting layer output connecting point are arranged on the surface of the silicon connecting layer in an array structure; a signal path structure communicated between the silicon connection layer input connection point and the corresponding silicon connection layer output connection point is distributed in the silicon connection layer;
a plurality of bare chip input connection points and a plurality of bare chip output connection points are preset on the surface of the test bare chip, the bare chip input connection points and the bare chip output connection points are arranged on the surface of the test bare chip in an array structure, and the relative arrangement structure between the connection points on the surface of the test bare chip is matched with the relative arrangement structure between the connection points on the silicon connection layer;
the inside of the test bare chip is also provided with JTAG control logic and a plurality of boundary scanning cell structures, each boundary scanning cell structure comprises a data input end, a data output end, a scanning input end and a scanning output end, each boundary scanning cell structure corresponds to one connecting point on the surface of the test bare chip respectively, the data input end of the boundary scanning cell structure corresponding to the bare chip input connecting point is connected with the bare chip input connecting point, and the data output end of the boundary scanning cell structure corresponding to the bare chip output connecting point is connected with the bare chip output connecting point; each boundary scanning cell structure is connected with the adjacent boundary scanning cell structure through a scanning input end and a scanning output end respectively, so that each boundary scanning cell structure is sequentially connected in series to form a boundary scanning test chain, and two ends of the formed boundary scanning test chain are connected to the JTAG control logic;
the test bare chip is arranged on the carrier, the connection points on the surface of the test bare chip are respectively attached to the connection points on the surface of the silicon connection layer, the input connection points of each bare chip are respectively butted with the output connection points of each silicon connection layer, and the output connection points of each bare chip are respectively butted with the input connection points of each silicon connection layer; and the JTAG control logic inside the test bare chip carries out test excitation transmission and test result capture on the connection point in the silicon connection layer through the boundary scan test chain so as to realize the test of the internal signal path structure of the silicon connection layer.
2. The silicon-link layer test circuit of claim 1, wherein the JTAG control logic within the test die transmits test stimuli to the boundary-scan cell structures connected to respective die output connection points via the boundary-scan test chain to corresponding silicon-link layer input connection points, the test stimuli being communicated to the corresponding silicon-link layer output connection points and to the boundary-scan cell structures connected to the corresponding die input connection points via signal path structures between the silicon-link layer internal connection points to form test results, the test results being transmitted to the JTAG control logic via the boundary-scan test chain.
3. The silicon connection layer test circuit of claim 2, wherein the silicon connection layer test circuit comprises a plurality of test dies, each test die is arranged on the carrier, the connection points on the surface of each test die are respectively attached to the corresponding connection points on the surface of the silicon connection layer, and all the test dies cover all the connection points on the surface of the silicon connection layer;
and the JTAG control logic in any first test die transmits test excitation to the boundary scan cell structure connected with each die output connection point through the boundary scan test chain so as to transmit the test excitation to the corresponding silicon connection layer input connection point, the test excitation is transmitted to the corresponding silicon connection layer output connection point through a signal path structure between the silicon connection layer internal connection points and is transmitted to the boundary scan cell structure connected with the die input connection point in the corresponding second test die to form a test result, the test result is transmitted to the JTAG control logic in the second test die through the boundary scan test chain in the second test die, and a plurality of test dies jointly complete the test of the silicon connection layer.
4. The silicon connection layer test circuit of claim 3, wherein each of the test dies is further provided with a test interface for connecting the internal JTAG control logic, the test interface at least comprises a data input terminal and a data output terminal, and the JTAG control logic inside each test die is sequentially connected in series through the data input terminal and the data output terminal.
5. The silicon connection layer test circuit of claim 2, wherein the test die is further provided therein with a stimulus generation circuit and a test response analysis circuit connected to the boundary scan test chain, the JTAG control logic generates the test stimulus according to the test vector generated by the stimulus generation circuit, and the JTAG control logic obtains the test result and transmits the test result to the test response analysis circuit to compare the expected test result corresponding to the test vector with the actually obtained test result, thereby completing the test on the silicon connection layer.
6. The silicon connection layer test circuit of claim 2, wherein the test die is further provided with a test interface for connecting an internal JTAG control logic, and the test die is connected to an external ATE tester through the test interface, the external ATE tester generates the test stimulus according to the test vector and outputs the test stimulus to the JTAG control logic through the test interface, the JTAG control logic formats and outputs the test result to the external ATE tester, and the external ATE tester compares an expected test result corresponding to the test vector with an actually obtained test result to complete the test on the silicon connection layer.
7. The SOWC test circuit of any of claims 1-6, wherein each of the boundary-scan cell structures within the test die includes a first multiplexer, a second multiplexer, a capture register, and an update register, wherein a data input of the boundary-scan cell structure is connected to one input of the first multiplexer and one input of the second multiplexer, a scan input of the boundary-scan cell structure is connected to another input of the first multiplexer, an output of the first multiplexer is connected to an input of the capture register, an output of the capture register is connected to an input of the update register and a scan output of the boundary-scan cell structure, and an output of the update register is connected to another input of the second multiplexer, the output end of the second multiplexer is connected with the data output end of the boundary scanning cell structure.
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| US20170242069A1 (en) * | 2011-06-20 | 2017-08-24 | Texas Instruments Incorporated | Testing interposer method and apparatus |
| CN111106092A (en) * | 2018-10-26 | 2020-05-05 | 三星电子株式会社 | Semiconductor package including test pad and method of forming the same |
| CN110007217A (en) * | 2019-05-22 | 2019-07-12 | 哈尔滨工业大学（威海） | A kind of low-power consumption boundary scanning test method |
| CN110780183A (en) * | 2019-10-16 | 2020-02-11 | 中国航空工业集团公司洛阳电光设备研究所 | Interface circuit for JTAG boundary scan test |
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