SG10202003905SA - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- SG10202003905SA SG10202003905SA SG10202003905SA SG10202003905SA SG10202003905SA SG 10202003905S A SG10202003905S A SG 10202003905SA SG 10202003905S A SG10202003905S A SG 10202003905SA SG 10202003905S A SG10202003905S A SG 10202003905SA SG 10202003905S A SG10202003905S A SG 10202003905SA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/88—Dummy elements, i.e. elements having non-functional features
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190094345A KR20210016214A (en) | 2019-08-02 | 2019-08-02 | Semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202003905SA true SG10202003905SA (en) | 2021-03-30 |
Family
ID=74165588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202003905SA SG10202003905SA (en) | 2019-08-02 | 2020-04-28 | Semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (2) | US11233062B2 (en) |
JP (1) | JP2021027331A (en) |
KR (1) | KR20210016214A (en) |
CN (1) | CN112310096A (en) |
DE (1) | DE102020108091B4 (en) |
SG (1) | SG10202003905SA (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210016214A (en) * | 2019-08-02 | 2021-02-15 | 삼성전자주식회사 | Semiconductor devices |
KR20210158449A (en) * | 2020-06-23 | 2021-12-31 | 삼성전자주식회사 | Semiconductor devices |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8786007B2 (en) | 2008-12-03 | 2014-07-22 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory device |
KR101145318B1 (en) * | 2010-07-15 | 2012-05-14 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabrication the same |
KR101519130B1 (en) | 2010-10-05 | 2015-05-12 | 삼성전자주식회사 | Nonvolatile memory device and method of forming the same |
KR102150253B1 (en) | 2014-06-24 | 2020-09-02 | 삼성전자주식회사 | Semiconductor device |
US10847540B2 (en) * | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
JP6495838B2 (en) | 2016-01-27 | 2019-04-03 | 東芝メモリ株式会社 | Semiconductor memory device and manufacturing method thereof |
KR102632478B1 (en) | 2016-09-02 | 2024-02-05 | 에스케이하이닉스 주식회사 | Semiconductor device |
US10483277B2 (en) * | 2016-09-13 | 2019-11-19 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing the same |
US9881929B1 (en) | 2016-10-27 | 2018-01-30 | Sandisk Technologies Llc | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof |
KR102650995B1 (en) | 2016-11-03 | 2024-03-25 | 삼성전자주식회사 | Vertical type memory device |
US10115632B1 (en) | 2017-04-17 | 2018-10-30 | Sandisk Technologies Llc | Three-dimensional memory device having conductive support structures and method of making thereof |
KR102373818B1 (en) | 2017-07-18 | 2022-03-14 | 삼성전자주식회사 | Semiconductor devices |
KR102366971B1 (en) | 2017-08-08 | 2022-02-24 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
US10685914B2 (en) | 2017-08-31 | 2020-06-16 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
KR102587973B1 (en) | 2017-11-07 | 2023-10-12 | 삼성전자주식회사 | Three-dimensional semiconductor devices |
KR102362622B1 (en) * | 2018-02-23 | 2022-02-14 | 삼성전자주식회사 | Semiconductor device including different types of memory cells |
US10943913B2 (en) * | 2018-09-27 | 2021-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strap-cell architecture for embedded memory |
US10847523B1 (en) * | 2019-07-03 | 2020-11-24 | Macronix International Co., Ltd. | Stacked memory and ASIC device |
KR20210016214A (en) * | 2019-08-02 | 2021-02-15 | 삼성전자주식회사 | Semiconductor devices |
-
2019
- 2019-08-02 KR KR1020190094345A patent/KR20210016214A/en not_active Application Discontinuation
-
2020
- 2020-03-24 DE DE102020108091.3A patent/DE102020108091B4/en active Active
- 2020-03-24 US US16/827,778 patent/US11233062B2/en active Active
- 2020-04-28 SG SG10202003905SA patent/SG10202003905SA/en unknown
- 2020-06-17 JP JP2020104598A patent/JP2021027331A/en active Pending
- 2020-07-31 CN CN202010756111.0A patent/CN112310096A/en active Pending
-
2022
- 2022-01-21 US US17/580,811 patent/US11637110B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
DE102020108091A1 (en) | 2021-02-04 |
US20210035991A1 (en) | 2021-02-04 |
US11233062B2 (en) | 2022-01-25 |
US20220149056A1 (en) | 2022-05-12 |
JP2021027331A (en) | 2021-02-22 |
CN112310096A (en) | 2021-02-02 |
DE102020108091B4 (en) | 2024-06-13 |
KR20210016214A (en) | 2021-02-15 |
US11637110B2 (en) | 2023-04-25 |
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