SE8902633D0 - Foerdroejningselement - Google Patents

Foerdroejningselement

Info

Publication number
SE8902633D0
SE8902633D0 SE8902633A SE8902633A SE8902633D0 SE 8902633 D0 SE8902633 D0 SE 8902633D0 SE 8902633 A SE8902633 A SE 8902633A SE 8902633 A SE8902633 A SE 8902633A SE 8902633 D0 SE8902633 D0 SE 8902633D0
Authority
SE
Sweden
Prior art keywords
delay elements
controlled
delay
clock
circuit
Prior art date
Application number
SE8902633A
Other languages
English (en)
Other versions
SE8902633L (sv
Inventor
L Morales
Original Assignee
Standard Microsyst Smc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Microsyst Smc filed Critical Standard Microsyst Smc
Publication of SE8902633D0 publication Critical patent/SE8902633D0/sv
Publication of SE8902633L publication Critical patent/SE8902633L/sv

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015Layout of the delay element
    • H03K2005/00195Layout of the delay element using FET's
SE8902633A 1988-08-02 1989-08-01 Foerdroejningselement SE8902633L (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/227,731 US4899071A (en) 1988-08-02 1988-08-02 Active delay line circuit

Publications (2)

Publication Number Publication Date
SE8902633D0 true SE8902633D0 (sv) 1989-08-01
SE8902633L SE8902633L (sv) 1990-02-03

Family

ID=22854237

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8902633A SE8902633L (sv) 1988-08-02 1989-08-01 Foerdroejningselement

Country Status (7)

Country Link
US (1) US4899071A (sv)
JP (1) JPH02141123A (sv)
CA (1) CA1291541C (sv)
DE (1) DE3924593A1 (sv)
FR (1) FR2635239A1 (sv)
GB (1) GB2222334A (sv)
SE (1) SE8902633L (sv)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140202A (en) * 1989-06-05 1992-08-18 Hewlett-Packard Company Delay circuit which maintains its delay in a given relationship to a reference time interval
US5144173A (en) * 1989-06-30 1992-09-01 Dallas Semiconductor Corporation Programmable delay line integrated circuit having programmable resistor circuit
US5160863A (en) * 1989-06-30 1992-11-03 Dallas Semiconductor Corporation Delay circuit using primarily a transistor's parasitic capacitance
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
US5164677A (en) * 1990-01-16 1992-11-17 Digital Equipment Corporation Method and apparatus for synchronizing signals
US5192886A (en) * 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
JP2597739B2 (ja) * 1990-08-24 1997-04-09 株式会社東芝 信号遅延回路、クロック信号発生回路及び集積回路システム
DE69130043T2 (de) * 1990-09-18 1999-04-15 Fujitsu Ltd Elektronische Anordnung mit einem Bezugsverzögerungsgenerator
JPH04157379A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 遅延測定方式
US5231319A (en) * 1991-08-22 1993-07-27 Ncr Corporation Voltage variable delay circuit
US5231320A (en) * 1991-09-16 1993-07-27 Motorola, Inc. CMOS delay line having duty cycle control
US5317219A (en) * 1991-09-30 1994-05-31 Data Delay Devices, Inc. Compensated digital delay circuit
DE69225040T2 (de) * 1991-11-01 1998-11-19 Hewlett Packard Co CMOS-pseudo-NMOS programmierbares Kapazitäts-Zeitvernierssystem und Verfahren zur gesteuerten Verzögerung von Zeitflanken
US5243227A (en) * 1991-11-01 1993-09-07 Hewlett-Packard Company Fine/coarse wired-or tapped delay line
US5233637A (en) * 1991-11-01 1993-08-03 Hewlett-Packard Company System for generating an analog regulating voltage
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5283631A (en) * 1991-11-01 1994-02-01 Hewlett-Packard Co. Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
JP2937591B2 (ja) * 1991-12-09 1999-08-23 沖電気工業株式会社 基板バイアス発生回路
US5220216A (en) * 1992-01-02 1993-06-15 Woo Ann K Programmable driving power of a CMOS gate
US5227679A (en) * 1992-01-02 1993-07-13 Advanced Micro Devices, Inc. Cmos digital-controlled delay gate
US5298866A (en) * 1992-06-04 1994-03-29 Kaplinsky Cecil H Clock distribution circuit with active de-skewing
US5349612A (en) * 1992-06-19 1994-09-20 Advanced Micro Devices, Inc. Digital serializer and time delay regulator
JP2951802B2 (ja) * 1992-08-07 1999-09-20 シャープ株式会社 クロック発生回路
US5650739A (en) * 1992-12-07 1997-07-22 Dallas Semiconductor Corporation Programmable delay lines
US5408200A (en) * 1992-12-18 1995-04-18 Storage Technology Corporation Intelligent phase detector
US5585754A (en) * 1993-04-02 1996-12-17 Nec Corporation Integrated digital circuit
US5430393A (en) * 1993-05-10 1995-07-04 Motorola, Inc. Integrated circuit with a low-power mode and clock amplifier circuit for same
JP3267756B2 (ja) * 1993-07-02 2002-03-25 株式会社日立製作所 半導体集積回路装置
DE4326062C1 (de) * 1993-08-03 1994-08-18 Siemens Ag Phasenregelanordnung
TW253083B (sv) * 1993-10-05 1995-08-01 Advanced Micro Devices Inc
US5491673A (en) * 1994-06-02 1996-02-13 Advantest Corporation Timing signal generation circuit
US5900761A (en) * 1995-01-24 1999-05-04 Advantest Corporation Timing generating circuit and method
US5489864A (en) * 1995-02-24 1996-02-06 Intel Corporation Delay interpolation circuitry
JP3557275B2 (ja) * 1995-03-29 2004-08-25 株式会社ルネサステクノロジ 半導体集積回路装置及びマイクロコンピュータ
US5719514A (en) * 1995-03-31 1998-02-17 Ando Electric Co., Ltd. Delay circuit compensating for variations in delay time
US5673005A (en) * 1995-08-18 1997-09-30 International Business Machine Corporation Time standard circuit with delay line oscillator
KR0146082B1 (ko) * 1995-09-22 1998-12-01 문정환 프로그래머블 아날로그 스위치
KR0172758B1 (ko) * 1995-12-29 1999-03-30 김주용 주파수의 주기조절이 가능한 주파수발생기
TW340262B (en) * 1996-08-13 1998-09-11 Fujitsu Ltd Semiconductor device, system consisting of semiconductor devices and digital delay circuit
US5994937A (en) * 1996-11-06 1999-11-30 International Business Machines Corporation Temperature and power supply adjusted address transition detector
US6236695B1 (en) * 1999-05-21 2001-05-22 Intel Corporation Output buffer with timing feedback
US6181185B1 (en) * 1999-07-14 2001-01-30 Agilent Technologies Low mismatch complementary clock generator
JP3365358B2 (ja) * 1999-07-23 2003-01-08 日本電気株式会社 クロック信号制御回路及び方法並びに同期遅延回路
US6377102B2 (en) * 2000-02-29 2002-04-23 Texas Instruments Incorporated Load equalization in digital delay interpolators
US6339354B1 (en) * 2000-04-03 2002-01-15 Mosel Vitelic, Inc. System and method for eliminating pulse width variations in digital delay lines
US6549081B1 (en) * 2000-07-27 2003-04-15 Agilent Technologies, Inc. Integrator/ comparator control of ring oscillator frequency and duty cycle
EP1286469A1 (en) * 2001-07-31 2003-02-26 Infineon Technologies AG An output driver for integrated circuits and a method for controlling the output impedance of an integrated circuit
US6580304B1 (en) * 2002-03-28 2003-06-17 M/A-Com, Inc. Apparatus and method for introducing signal delay
JP3762988B2 (ja) * 2002-07-09 2006-04-05 独立行政法人産業技術総合研究所 クロック信号タイミング調整のための遅延回路を有するデジタル回路
US20040222832A1 (en) * 2003-05-09 2004-11-11 Chaiyuth Chansungsan Interpolator circuit
US7515669B2 (en) * 2005-09-15 2009-04-07 Etron Technology, Inc. Dynamic input setup/hold time improvement architecture
TWI358902B (en) * 2007-12-31 2012-02-21 Ind Tech Res Inst Signal delay circuit
US9252759B1 (en) * 2014-09-03 2016-02-02 United Memories, Inc. Linear progression delay register
US9350338B2 (en) * 2014-09-03 2016-05-24 United Memories, Inc. Linear progression delay register
US10284188B1 (en) 2017-12-29 2019-05-07 Texas Instruments Incorporated Delay based comparator
US10673452B1 (en) 2018-12-12 2020-06-02 Texas Instruments Incorporated Analog-to-digital converter with interpolation
US10673456B1 (en) 2018-12-31 2020-06-02 Texas Instruments Incorporated Conversion and folding circuit for delay-based analog-to-digital converter system
US11316526B1 (en) 2020-12-18 2022-04-26 Texas Instruments Incorporated Piecewise calibration for highly non-linear multi-stage analog-to-digital converter
US11387840B1 (en) 2020-12-21 2022-07-12 Texas Instruments Incorporated Delay folding system and method
US11309903B1 (en) * 2020-12-23 2022-04-19 Texas Instruments Incorporated Sampling network with dynamic voltage detector for delay output
US11438001B2 (en) 2020-12-24 2022-09-06 Texas Instruments Incorporated Gain mismatch correction for voltage-to-delay preamplifier array
US11962318B2 (en) 2021-01-12 2024-04-16 Texas Instruments Incorporated Calibration scheme for a non-linear ADC
US11316525B1 (en) 2021-01-26 2022-04-26 Texas Instruments Incorporated Lookup-table-based analog-to-digital converter
US11881867B2 (en) 2021-02-01 2024-01-23 Texas Instruments Incorporated Calibration scheme for filling lookup table in an ADC

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737673A (en) * 1970-04-27 1973-06-05 Tokyo Shibaura Electric Co Logic circuit using complementary type insulated gate field effect transistors
US3914702A (en) * 1973-06-01 1975-10-21 Rca Corp Complementary field-effect transistor amplifier
US3855549A (en) * 1973-08-24 1974-12-17 Rca Corp Circuit, such as cmos crystal oscillator, with reduced power consumption
DE2855724A1 (de) * 1978-12-22 1980-07-03 Ibm Deutschland Verfahren und vorrichtung zur angleichung der unterschiedlichen signalverzoegerungszeiten von halbleiterchips
US4346343A (en) * 1980-05-16 1982-08-24 International Business Machines Corporation Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay
JPS5949020A (ja) * 1982-09-13 1984-03-21 Toshiba Corp 論理回路
EP0390226A1 (en) * 1984-07-31 1990-10-03 Yamaha Corporation Jitter absorption circuit
US4700089A (en) * 1984-08-23 1987-10-13 Fujitsu Limited Delay circuit for gate-array LSI
DE3676297D1 (de) * 1986-03-12 1991-01-31 Itt Ind Gmbh Deutsche Integrierte isolierschicht-feldeffekttransistor-verzoegerungsleitung fuer digitalsignale.
JPS6324712A (ja) * 1986-07-17 1988-02-02 Toshiba Corp Mos型半導体回路
JPS6346011A (ja) * 1986-08-13 1988-02-26 Hitachi Ltd 遅延回路
JPS6369314A (ja) * 1986-09-11 1988-03-29 Sony Corp Cmos回路を用いた可変遅延装置
GB2197553A (en) * 1986-10-07 1988-05-18 Western Digital Corp Phase-locked loop delay line
JPH0740437B2 (ja) * 1986-11-19 1995-05-01 日本電気株式会社 遅延回路
US4771196A (en) * 1987-08-05 1988-09-13 California Institute Of Technology Electronically variable active analog delay line

Also Published As

Publication number Publication date
GB8917247D0 (en) 1989-09-13
JPH02141123A (ja) 1990-05-30
US4899071A (en) 1990-02-06
GB2222334A (en) 1990-02-28
CA1291541C (en) 1991-10-29
SE8902633L (sv) 1990-02-03
FR2635239A1 (fr) 1990-02-09
DE3924593A1 (de) 1990-02-08

Similar Documents

Publication Publication Date Title
SE8902633L (sv) Foerdroejningselement
ES383650A3 (es) Perfeccionamientos en detectores de diferencia de fase.
DE69218537T2 (de) CMOS-Ausgangspufferschaltung mit wählbarem Flankenanstieg
DE3889650D1 (de) Integrierte Halbleiterschaltung mit einem Eingangsspannungsbegrenzer.
DE3783139D1 (de) Verbesserungen bezueglich und in abhaengigkeit von aufzeichnung und ausgabe von beweglichen fernsehbildern.
KR880005746A (ko) 반도체집적회로
KR950700637A (ko) 선택가능한 출력지연을 갖는 자기보상형 디지탈지연반도체장치와 그 방법
DE68919404T2 (de) Halbleiterspeicher mit Serieneingang/Serienausgang.
SE9003851L (sv) Detektor av typen med reglerad spaenning och tvaa ledare eller traadar
DE3171351D1 (en) Improvements in or relating to electronic clock generators
DE68908318D1 (de) Halbleiterspeicher mit serieneingang/serienausgang.
KR970031263A (ko) 정합필터회로(matched filter circuti)
DE68914073T2 (de) Integrierte Speicherschaltung mit parallelem und seriellem Ein- und Ausgang.
ATE44848T1 (de) Ladungsgekoppelte halbleiteranordnung mit dynamischer steuerung.
DE69126694T2 (de) Integrierte Halbleiterschaltung mit ECL-Eingangs- Ausgangspuffern
DE69025618D1 (de) Eingangs/ausgangsmodul mit eingangs/ausgangskombinationspunkt
JPS5632824A (en) Pulse eliminating circuit
SE9501608D0 (sv) Generator för fördröjningsanpassade klock- och datasignaler
DE3670410D1 (de) Digitaler differenzfrequenzmischer.
JPS5475525A (en) Electric source device
SE8505870D0 (sv) Styrkrets
SU1007039A1 (ru) Устройство дл измерени напр жени
US5012085A (en) Self adaptive and shadow sensitive electronic musical instrument
UA12252A1 (uk) Пристрій корекції виділеhhя осhовhого тоhу
FR2433263A1 (fr) Agencement de circuit pour le declenchement de composants a declenchement par un bord

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 8902633-0

Effective date: 19930301

Format of ref document f/p: F