SE1251089A1 - Kemiskt pläterad metallvia genom kisel - Google Patents

Kemiskt pläterad metallvia genom kisel Download PDF

Info

Publication number
SE1251089A1
SE1251089A1 SE1251089A SE1251089A SE1251089A1 SE 1251089 A1 SE1251089 A1 SE 1251089A1 SE 1251089 A SE1251089 A SE 1251089A SE 1251089 A SE1251089 A SE 1251089A SE 1251089 A1 SE1251089 A1 SE 1251089A1
Authority
SE
Sweden
Prior art keywords
silicon
poly
substrate
layer
depositing
Prior art date
Application number
SE1251089A
Other languages
English (en)
Other versions
SE538062C2 (sv
Inventor
Henrik Knutsson
Thorbjörn Ebefors
Original Assignee
Silex Microsystems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silex Microsystems Ab filed Critical Silex Microsystems Ab
Priority to SE1251089A priority Critical patent/SE538062C2/sv
Priority to US14/431,002 priority patent/US9514985B2/en
Priority to PCT/SE2013/051124 priority patent/WO2014051511A2/en
Priority to EP13841291.1A priority patent/EP2901475B1/en
Publication of SE1251089A1 publication Critical patent/SE1251089A1/sv
Priority to HK16100996.6A priority patent/HK1213089A1/zh
Priority to US15/040,148 priority patent/US9613863B2/en
Publication of SE538062C2 publication Critical patent/SE538062C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2782—Applying permanent coating, e.g. in-situ coating
    • H01L2224/27825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)

Abstract

SAMMANDRAG Uppfinningen avser en metod att tillverka en substratgenomgaende via med Mgt djup/vidd-forhallande, i ett halvledarsubstrat, och ett metallmOnster pa substratytan. Den innefattar tillhandahallande av ett halvledarsubstrat (skiva) och att deponera polykisel pa substratet. Polykislet pa substratets yta mOnstras genom att etsa bort oonskade partier. Darefter deponeras Ni selektivt pa polykislet medelst en kemisk plateringsprocess. Ett viahal Ors genom substratet, dar halets vaggar utsatts for samma processning som ovan. Cu deponeras Ni medelst en kemisk plateringsprocess. 10 (Figur 14)

Description

KEMISKT PLATERAD METALL VIA GENOM K1SEL Uppfinningens omrade Uppfinningen avser kiselgenomgdende viateknologi (TSV), och speciellt att tillhandhaalla 5 metallvior med stort fOrhallande mellan djup och vidd i substrat tillsammans med sjalvlinjerande "ledningsdragning"-strukturer pa ytan av substratet for att tillverka s.k. interposrar.
Uppfinningens bakgrund I stravan att Ora komponenter mindre och mindre speciellt ffir att stapla chip i tre dimensioner maste awn s.k. substratgenomgdende vior (eller kiselgenomgdende vior specifikt), vilka anvands for att leda ut signaler fran en sida av ett substrat till en annan, bli mindre och tatare packade. Detta kommer att ha som konsekvens att forhallandet mellan vidd och djup blir hogre, dvs. D/W>5.
De sputtringstekniker som vanligtvis anvands for att tillhandahalla metallvior är inte gangbara for forhallanden av den storleksordningen, eftersom de resulterar i icke-konform deponering, vilket i sin tur orsakar problem i att uppna lämplig "stegtackning" pa vaggarna. Teknologier som ger battre stegtackning sasom ALD, (MO)CVD och andra är dyrbara, langsamma och kan inte anvandas for satsvis korning. Ovanstaende negativa effekter är det som fororsakar problemen i att erhalla ldmplig vidhaftning av barridr- och saddlager for pldtering. Dessa teknologier kraver dessutom ofta ensidig processning av skivor vilket resulterar i ett behov av komplexa bdrarskivlosningar om skivorna innefattar oppna skivgenomgaende hal.
For blinda viahal med Mgt djup/vidd-forhallande foreligger ocksa ett problem da elektrodeponering anvands i det att det är svart att tillhandahalla lämplig vatning av Mien och det är darfor svart att f ned kemin i Hien pa ett lampligt salt.
Vidare är det onskvart att tillhandahalla yteffektiva och smala elektriska ledningsdragningsmonster (eller "routings") pa substratytan for att leda ut signaler till och fran komponenter pa substratet genom substratet med anvandning av viorna. Sadana ledningsdragnigsmonster kan vara tamligen komplicerade att processa och kraver ofta flera litografiska steg, och !eller CMP (kemisk mekanisk polering) som är en dyrbar procedur. Vatetsning av saddlager och barriarlager är ofta tamligen komplex, om det maste utforas efter elektropldtering av koppar. Se t.ex. en artikel av Richard et al, "Barrier and Copper Seed Layer Wet Etching" i Solid State Phenomena, Vol. 103-104, 2005, sid. 361-364.
I EP 1 987 535 (Silex) beskrivs en metod att tillverka metallvior med anyandning av guld.
I ljuset av att guld är ett mycket dyrbart material är denna metod inte sarskilt ekonomiskt gangbar.
I WO 2010/133550 (Alchimer) beskrivs en metod att tillverka ett belagt substrat, ddr ett halrum tillverkas i en substratyta genom etsning. Ett isolerande dielektriskt skikt deponeras pa substratytan och darefter deponeras polykisel, som dopats in situ med fosfor, pa det dielektriska skiktet. Slutligen elektrodeponeras koppar pa det dopade polykislet. Ingen koppardiffusionsbarriar tillhandahalls i denna process.
I sokandens egen WO 2010/059188 Al uppnas samtidig "sjalvupplinjering" av ledningsdragning och viafyllning, men med de tekniker som är tillgangliga idag ger detta linjevidder >10 [tm, atminstone i kostnadseffektiv volymproduktion.
Sammanfattning av uppfinningen Syftet med uppfinningen är att tillhandahalla en metod som far bukt med nackdelarna som antytts i bakgrundsavsnittet och som mOjliggOr tillhandahallande av konforma metallbelaggningar med god vidhaftning i kombination med koppardiffusionsbarrarlager, i viahal med Mgt fOrhallande mellan djup och vidd, och som i samma process tillhandahaller sjalvlinjerande ledningsdragningsmOnster med farre steg an i enlighet med de kanda metoderna. Detta uppnas med en metod baserad pa kemisk platering med anvandning av oppna viahâl, och definieras i krav 1.
I en forsta utforingsform tillhandahaller metoden "sjalvupplinjering" av ledningsdragningmonster av metall och god vidhaftning for materialen, eftersom dessa monster definieras i polykisel pa vilket barriar- och saddlager deponeras selektivt, och ingen etsning av saddlager eller barriar krays fore eller efter att den slutliga metalliseringen tillhandahalles. Kemisk platering utfors i oppna viahâl, dvs. hal som stacker sig genom hela substratet, vilket gOr det latt att tillhandahalla den nodvandiga omrorningen av plateringslosningar.
Alternativt mojliggor uppfinningen elektroplatering av metalliseringen, med anvandning av polykisel sasom ledande skikt, lampligen skyddad med oxid for att lamna endast onskade ytor exponerade for platering.
Foredragna utforingsformer definieras i beroende krav.
En stor fordel med foreliggande uppfinning är att den mojliggor satsvis processning av skivor i motsats till kanda metoder dar individuella skivor processade en och en, vilket gOr processen mycket kostnadseffektiv genom samtidig dubbelsidig processning. Oppna vior forbattrar vatningsformagan under platering, vilket far bukt med nackdelarna med metoderna enligt teknikens standpunkt. Den mojliggor ocksa tillverkning av styva TSVskivor med hermetiskt forseglade viastrukturer.
Ytterligare tillampningar av uppfinningen kommer att framgâ av den detaljerade beskrivningen som ges i det foljande och de bifogade ritningarna vilka endast ges i illustererande syfte och saledes inte ska betraktas som begransande av uppfinningen och i vilka Kort beskrivning av bifogade ritningar Fig. 1-7 illustrerar en processekvens av en utforingsform av en metod; Fig. 8-14 illustrerar en processekvens av en annan utforingsform av en metod; Fig. 15 visar schematiskt elektroplatering av en struktur fran fig. 14; och Fig. 16a-b illustrerar uppfinningen med anvandning av olika viatyper.
Detaljerad beskrivning av foredragna utf6ringsformer Foreliggande uppfinning tillhandahaller en metod att astadkomma en konform metallbelaggning i vior med Mgt forhallande mellan djup och vidd. Detta astadkommes genom att anvanda en kemisk deponering av koppar pa en bas av polykisel med dopning av n-typ (t.ex. fosfor) valfritt med ett nickelbarriarlager som ocksa tillhandahalles med kemisk deponering. Dessutom tillhandahalles i samma deponeringssteg sjalvlinjerad ledningsdragning.
Metoden kommer nu att beskrivas med hanvisning till ritningsfigurema.
Som visas i fig. 1 tillhandahalles saledes ett substrat 10, fbretradesvis en skiva av ett halvledarmaterial, lampligtvis enkristallint kisel, aven om andra material vanliga vid processning Mom MEMS/IC är anvandbara.
Med hanvisning till fig. 2 Ors ett genomgaende hal 12 i substratet med valkanda processer, t.ex. genom litografi som involverar att man tillhandahaller en resist pa ytan, exponerar ett monster motsvarande de hal som ska goras, och framkallning av resisten (ej visad). Darefter utfors en etsning varvid ett hal 12 tillverkas.
Hela substratet passiveras, foretradesvis medelst oxidation, sasom visas i fig. 3, sa att ytoma 14, 16 pa substratet och aven vaggarna 18 i halet 12 tacks med ett tunt oxidskikt 20. Oxidens tjocklek är> 0,5 pm, typiskt omkring 1 pm.
Darefter deponeras polykisel over substratet till bildande av ett polykiselskikt 22 som tacker hela substratet inkluderande vaggama 18 i halet 12, sasom kan ses i fig. 4. En konform deponeringsteknik sasom LPCVD (Low Pressure Chemical Vapour Deposition) foredras pga av dess goda likformiga tackning pa halen med hogt djup/viddforhallande.
Polykislet dopas valfritt, foretradesvis med fosfor, antingen i en deponeringsprocess eller efterat medelst en dopningsdiffusionsprocess eller jonimplanteringsprocess med efterfoljande varmebehandling/aktivering.
Nu monstras polykislet med anvandning av liknande eller samma tekniker som tidigare, dvs. litografi for att tillhandahalla en etsmask for att pa sa satt mojliggora att etsa bort oonskade partier av polykislet for attlamna kvar endast ytor 24 av polykislet 221ampliga for platering, fig. 5. Dessa ytor kan vara ledningsdragningsmonster eller andra strukturer pa ytan.
Nu skall ett saddlager for senare platering anordnas pa de polykiselomraden som kvarstar, lampligtvis med en kemisk deponering av koppar. Emellertid kravs ett barriarlager 26 mot koppardiffusion och en sadan barriar maste darfor fors paforas medelst kemisk deponering av nickel eller nickellegering, som selektivt kommer att belagga polykislet, se fig. 6. Koppar deponeras darefter med kemisk platering pa kislet.
For att forbattra vidhaftningen av nickelskiktet utfors lampligen en hogtemperatursilicidering med t.ex. en RTA-process (Rapid Thermo Annealing), lampligtvis vid 300-700°C. Detta kommer att bilda ett tunt mellanliggande skikt av silicid, SixNiy, dar x:y kan variera i intervallet 1:2 till 2:1 (den exakta kompositionen beror pa temperaturen), vilket ar kant for goda och stabila elektriska egenskaper och anvands ofta i t.ex. IC-processer som diffusionsbarriar. Silicidlagret visas sasom 27 i fig. 7 som ett tjockare gransyteskikt.
Manga andra TSV-processer inkluderar startsubstrat med metall vilket for dem mer begransade i termer av vilka processer och temperaturer som kan anvandas.
Om hermetiskt forseglade vior behovs plateras ett tjockare kopparlager 28 pa barridr- /saddlagret 27 med hjalp av en kemisk process varvid halet valfritt eventuellt fOrsluts och en solid metallvia formas i samma processteg som Onskad ledningsdragning eller andra strukturer som definieras pa ytan av substratet, se fig. 7.
Det bar noteras att denna utforingsform omfattar processning pa skivor som uppvisar topografi (dvs hal) vilket gar det nagot mer komplicerat, aven om det fortfarande resulterar i fordelaktiga sardrag jamfor med teknikens standpunkt.
I en annan utforingsform som är annu mer fordelaktig i det att den eliminerar behovet av litografi pa icke plana ytor, andras processekvensen nagot, hanvisning Ors till fig. 8-14. 20 Denna utforingsform medger mindre detaljstorlekar i ledningsdragningsstrukturerna.
En substratskiva 30 tillhandahalles sasom tidigare, men nu oxideras hela skivan 32, dar tjockleken av oxiden är> 0,5 [tm, typiskt ungefar 1-3 pm. Oxiden tacks av ett skyddande SN-skikt 34 som är jamforelsevis tjockt (dvs > 0,1 [im tjockt). SiN kommer att skydda oxiden i senare processteg. Darefter deponeras ett tamligen tjockt (> 2 tm tjockt) polykiselskikt 36, over hela skivan, sasom visas i fig. 8.
Polykislet 36 pa det plana substratet, dvs utan topografi (inga hal) monstras med litografi for att tillhandahalla en struktur som motsvarar ledningsdragning pa ytan, om sa krays, och aven en oppning 37 tillhandahalles for etsning av det genomgaende halet, se fig. 9a-b (halet som skall tillverkas visas med streckad linje i fig. 9b). Tack vare att processningen utfors pa ett plant substrat ar det mojligt att uppna upplosning av- de fina detaljema ned till sub-m-omradet. Darefter pears ett ytterligare SiN-skikt 38, vilket lager ar tunnare an det skyddande SiN-skikt 34 som palagts tidigare, av skal som kommer att framga nedan.
Efter lamplig maskning, t.ex. genom att spinna pa en resist och anvanda fotolitografi for att avlagsna oonskade omraden, utfors en etsning pa skivan genom masken varigenom ett hal 39 etsas genom skivan, fig. 10a.
En lokaliserad termisk oxidation utfors varvid endast de exponerade kiselytorna oxideras, dvs vaggarna i det genomgaende halet belaggs med oxid 40, fig. 10b, dar oxidens tjocklek > 0,5 [tm, typiskt mellan 1-3 pm, medan de ytomraden som skyddas med SiN inte kommer att oxideras.
Nu utfors en etsning vilken kommer att avlagsna SiN 38 pa de horisontella ytorna och lamnar kvar det forsta SiN-lagret 34 och polykislet 36 exponeras, sasom visas i fig. 11.
For att emellertid kunna tillhandahalla ett bra saddlager som sakerstaller den slutliga belaggningen med metal! for aft bade fylla halet och tillhandahalla koppar pa ledningsdragningsstrukturema, och viktigast tillhandahalla elektrisk forbindelse mellan via och ledningsdragning, maste polykisel anordnas pa vaggarna i Met, och darfor deponeras polykisel 41 pa nytt over hela skivan, sasom visas i fig. 12. Polykiselskiktet 41 är typiskt tunnare an polykislet 36 som tillhandah011s tidigare i processen. Denna deponeringsprocess kommer att tacka skivans yta, antingen en sida eller valfritt bagge sidor, med polykisel, och salunda maste det selektivt avlagsnas fOr att exponera endast det polykisel 36 som definierar ledningsdragningsstrukturema, annars skulle hela ytan senare plateras med metal!.
For detta andamal utfcirs en biaserad ME pa ytan vilket avlagsnar den andra deponeringen av tunnare polykisel ned till nitrid-toxidlagret med undantag for de ytor som tacks av det forsta tjockare deponerade polykislet 36, varigenom man kommer fram till den struktur som visas i fig. 13 a. Etsningsprocessen stalls in sa att den endast etsar det andra polykislet pa de plana substratytoma, men attackerar inte det andra, vertikalt anordnade polykislet pa viavaggarna.
Ett mycket viktigt sardrag är det som visas i det inringade partiet, forstorat i fig. 13b, namligen att trots forekomsten av ett "avbrott" i kontinuiteten i polykiselskikten 34, 41, kommer det att vara mojligt att tillhandahalla ett kontinuerligt nickelskikt 42 genom kemisk platering som Ors selektivt pa polykiselytoma. I motsats till elektroplatering kommer den kemiska plateringen att fororsaka att nicklet tillvaxer sa att det nickel som avsatts pa de tvâ olika polykiselytoma slutligen kommer att "overbrygga" gapet och far bilda ett kontinuerligt skikt pa det deponerade nicklet. Nickel skiktet visas i fig. 13c.
Foretradesvis tillhandahalles nickellagret som en koppardiffusionsbarriar pa vilken darefter koppar kan plateras for att pa sa salt fylla halet och tillhandahalla kopparledningsdragning pa skivytan. Nicklet visas som skiktet 42 i fig. 14 och den platerade kopparen visas som 43. Det är ett viktigt sardrag hos uppfinningen att den platerade kopparen 43 ar kontinuerlig, dvs att det inte finns flagon distinkt gransyta mellan den horisontellt palcirda kopparen och kopparen inuti vian. Anyo skulle silicidering till bildande av SixNiy, sasom beskrivits tidigare, kunna utforas for att forbdttra vidhaftning.
Den foredragna kemiska nickelpldteringen är kommersiellt tillgänglig och fosforbaserad, och for att erhalla basta resultat dopas darefter polykislet foretradesvis med fosfor.
Polykislet kan antingen dopas in situ eller A. kan det dopas i en separat dopningsprocess som involverar vdrmebehandling.
I utforingsformer som visats och beskrivits, processas endast den ovre (sett i figuren) sidan i substratet for att tillhandahalla ledningsdragning. Naturligtvis skulle emellertid bagge sidor av substratet kunna processas for att tillhandahalla och denna aspekt ligger ocksd Mom ramen for uppfinningstanken. lb land ar det onskvart att tillhandahalla 100 % hermetiskt tata vior, dvs. det fdr inte forekomma nagot ldckage mellan motstdende sidor av substratskivan genom viorna.
I de metoder som beskrivits ovan finns oundvikligen en risk att bubblor bildas under den kemiska pldteringen och denna bubbelbildning kan fororsaka ett problem i det att det kan bildas ett halrum i centrum av vian, vilket i varsta fall skulle kunna ge upphov till en kanal som ger upphov till icke-hermetisk tatning mellan motstaende sidor av substratskivan. Detta illustreras schematiskt med streckade linjer i fig. 15.
For att fOrhindra att detta sker och air att sakerstalla 100 % hermeticitet kan de metoder som beskrivs han, i en ytterligare utforingsform, kompletteras med ett tillkommande elektroplateringssteg som inte generar bubblor och som anvands till konventionella TSV av koppar, och som kommer att beskrivas i detalj nedan med hanvisning till fig. 15.
For att kunna lagga pa de erforderliga potentialerna pa de omildena som forplateras med kemisk platering maste man tillhandahalla elektrisk fOrbindelse mellan de omilden som skall plateras.
Saledes monstras inte det polykisel 36 som deponerats i tidigare steg och etsas for att definiera ledningsdragning, sasom beskrivits i anslutning till t.ex. fig. 9a, och i stallet tacks polykislet 36 selektivt med ett isolerande material 46, t.ex. oxid, i enlighet med ett onskat monster for att definiera ledningsdragningsmonstret, och kommer salunda att tacka endast de partiera som inte definierar ledningsdragning. Pa detta satt skyddar oxiden 46 polykislet frail att plateras (kemiskt platerat nickel- och kopparsaddlager), och endast de onskade ledningsdragningsmonstren och viastrukturerna kommer att belaggas med metall. Saledes kommer polykisel skiktet att verka sasom medel for att transportera strom till varje plats dar elektroplatering är onskvard. Hela skivan sanks ned i ett plateringsbad 47 och en negativ potential (likspanning) palaggs pa polykislet, oftast langs skivans kant, for att pa sà satt mojliggora reduktion av metall pa de stallen dar platering skall ske.
Forutom likstromsplatering kan olika typer av s.k. pulsplatering anvandas. En risk med likstromsplatering an att viahalen kan forseglas endast vid oppningen sâ att ett potentiellt halrum bildas inuti via. Med back pulsplatering kan detta fenomen reduceras och till och med elimineras.
Sarskilt fordelaktigt an det om viastrukturen an av den typ som beskrivs i EP 2 165 362 (ASTC Aerospace AB), som betecknas XiViaTM. Denna viastruktur innefattar en bred del och en smal del med sluttande ytor. Den smala delen är ungefar 25 [inn av skivtjockleken. Det finns vidare en "strypning" S i vian med mindre diameter (i storleksordningen < lam) som gOr det lattare och snabbare att fiirsegla och erhalla en hermetisk forslutning.
Skillnaden mellan en ordinar via och XiViaTM-typen av via illustreras schematiskt i fig. 16 (dimensionerna an inte skalenliga). I fig. 16a framgar det saledes tydligt att det finns ett tamligen stort omrade (den inre omkretsytan; vidd/diameter 50-75 tm, hallangdldjup 300400 [tm) som maste plateras och det kommer oundvikligen att ta en vasentlig tid att forsluta vian, vilket är ett problem i sig sjalvt, eftersom processtid är dyrbar. Ett annat problem an att plateringshastigheten an nagot snabbare vid kanterna E som antyds med en pil inuti vian, och som ett resultat forsluts vian vid "ingangarna" och darfor foreligger en risk att ett halrum kan bli resultatet. Ett sadant halrum V illustreras schematiskt med de streckade linjerna i fig. 16a. Vid anvandning och/eller processning kan detta halrum som innehaller restmaterial fran plateringen (vatska, gas) fororsaka sprickning av skivmaterialet och hermeticiteten kommer darfor att forloras. 7 I motsats till detta kommer vian (XiViaTM) som visas i fig. 16b att forslutas endast vid strypningen S och saledes kommer inget halrum att bildas och hermeticiteten garanteras.

Claims (19)

PATENTKRAV: 1. En metod RV att tillverka en substratgenomgaende via med Mgt sidalangdforhallande i ett halvledarsubstrat, och ett metallmonster pa substratytan, innefattande:
1. att tillhandahalla ett halvledarsubstrat (skiva); 2. att deponera polykisel pa substratet; 3. att mOnstra polykislet pa substratet genom att etsa bort oonskade partier; 4. att selektivt deponera Ni pa polykislet medelst en kemisk plateringsprocess; att Ora ett viahal genom substratet, dar vagarna i halet utsatts fOr samma behandling som substratet utsatts RV i stegen b) - d); att det deponerade Ni pa substratet och pa vaggarna i halet upphettas till ungefar 300-700 -C for att skapa SixNiy; och att deponera Cu pa Ni medelst en kemisk plateringsprocess.
2. Metod enligt krav 1, dar x:y ligger i intervallet 1:2 till 2:1.
3. Metod enligt krav 1, dar deponeringen av Cu fortsatts tills viahalet är slutet.
4. Metod enligt nagot av forega.ende krav, ytterligare innefattande oxidering av substratet innan polykisel deponeras.
5. Metod enligt nagot av foregaende krav, ytterligare innefattande monstring av polykislet och avldgsnande av oOnskade omraden av polykislet i enlighet med mOnstret.
6. Metod enligt nagot av fOrega.ende krav, ytterligare innefattande dopning av polykislet, foretradesvis med fosfor.
7. Metod enligt nagot av foregaende krav 4, eller enligt krav 5 eller 6 sasom beroende av krav 4, ytterligare innefattande deponering av ett fOrsta SiN-skikt pa oxiden.
8. Metod enligt krav 7, innefattande deponering av ytterligare ett SiN-skikt pa polykislet, ddr det ytterligare SiN-skiktet dr tunnare an det forsta SiN-skiktet.
9. Metod enligt krav 8, ytterligare innefattande att en mask anordnas pa det ytterligare SiN-skiktet for att definiera viahalet, och etsning genom masken for att Ora halet.
10. Metod enligt krav 9, ytterligare innefattande att vaggarna i viahalet oxideras.
11. Metod enligt krav 9, innefattande lokaliserad oxidering vid hog temperatur.
12. Metod enligt krav 8, ytterligare innefattande att det ytterligare SiN-skiktet avlagsnas fran substratet fOr att exponera polykisel och att ytterligare polykisel deponeras Over hela substratet inkluderande inuti viahale, ddr det ytterligare polykislet ãr tunnare an det tidigare anordnade polykislet, och att en ets ddrefter utfors for att avlagsna det ytterligare polykislet fran "field" ner till oxidskiktet, men ddr polykisel ldmnas kvar pa vaggarna i viahalet, for att astadkomma ett kontinuerligt polykiselskikt pa det definerade monstret och inuti halet.
13. Metod enligt krav 12, ytterligare innefattande att ett saddlager pafors pa polykislet RV efterfOljande kemisk platering, och att selektivt platera Cu pa saddlagret.
14. Metod enligt krav 12, ytterligare innefattande att en Cu-diffusionsbarriar anordnas innan saddlagret pafOrs.
15. Metod enligt krav 14, dar diffusionsbarriarlagret är Ni-baserat.
16. Metod enligt krav 15, ddr diffusionsbarridrlagret innefattar fosfordopat Ni.
17. Metod enligt krav 16, dar Ni-lagret ãr siliciderat.
18. Metod enligt krav 17, dar diffusionsbarridrlagret ocksa ãr ett adhesionslager. Z '61J / (.1 Z1, , I. .6u 17 .6u CN N- CN OZ171, 9 I- 9 '6U 4/12 z9 LC 8 .Bu Ze9C17C 37 38/ 34i r,------ I 36- 32 111 I
SE1251089A 2012-09-27 2012-09-27 Kemiskt pläterad metallvia genom kisel SE538062C2 (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE1251089A SE538062C2 (sv) 2012-09-27 2012-09-27 Kemiskt pläterad metallvia genom kisel
US14/431,002 US9514985B2 (en) 2012-09-27 2013-09-27 Electroless metal through silicon via
PCT/SE2013/051124 WO2014051511A2 (en) 2012-09-27 2013-09-27 Electroless metal through silicon via
EP13841291.1A EP2901475B1 (en) 2012-09-27 2013-09-27 Method for forming a through-silicon via by electroless metal deposition, and corresponding semiconductor device
HK16100996.6A HK1213089A1 (zh) 2012-09-27 2016-01-29 通過硅通孔的無電鍍金屬
US15/040,148 US9613863B2 (en) 2012-09-27 2016-02-10 Method for forming electroless metal through via

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE1251089A SE538062C2 (sv) 2012-09-27 2012-09-27 Kemiskt pläterad metallvia genom kisel

Publications (2)

Publication Number Publication Date
SE1251089A1 true SE1251089A1 (sv) 2014-03-28
SE538062C2 SE538062C2 (sv) 2016-02-23

Family

ID=50389103

Family Applications (1)

Application Number Title Priority Date Filing Date
SE1251089A SE538062C2 (sv) 2012-09-27 2012-09-27 Kemiskt pläterad metallvia genom kisel

Country Status (5)

Country Link
US (2) US9514985B2 (sv)
EP (1) EP2901475B1 (sv)
HK (1) HK1213089A1 (sv)
SE (1) SE538062C2 (sv)
WO (1) WO2014051511A2 (sv)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9716192B2 (en) 2014-03-28 2017-07-25 International Business Machines Corporation Method for fabricating a photovoltaic device by uniform plating on emitter-lined through-wafer vias and interconnects
JP6362254B2 (ja) * 2014-05-12 2018-07-25 国立大学法人東北大学 半導体装置およびその製造方法
JP6363868B2 (ja) * 2014-05-12 2018-07-25 国立大学法人東北大学 半導体装置およびその製造方法
KR102049724B1 (ko) * 2015-08-18 2019-11-28 미쓰비시덴키 가부시키가이샤 반도체 장치
KR102501675B1 (ko) 2018-07-13 2023-02-17 삼성전자주식회사 반도체 장치 및 그 제조 방법
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
CN112289688B (zh) * 2019-07-22 2024-05-07 盛合晶微半导体(江阴)有限公司 一种重新布线层的制备方法
US11862546B2 (en) * 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
CN113161290A (zh) * 2021-04-22 2021-07-23 浙江集迈科微电子有限公司 一种带有tsv金属柱的硅片结构的电镀工艺
CN115588652A (zh) * 2021-07-05 2023-01-10 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608264A (en) * 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
JP3305929B2 (ja) * 1995-09-14 2002-07-24 株式会社東芝 半導体装置及びその製造方法
US6180523B1 (en) * 1998-10-13 2001-01-30 Industrial Technology Research Institute Copper metallization of USLI by electroless process
US6853067B1 (en) 1999-10-12 2005-02-08 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
US20020179921A1 (en) 2001-06-02 2002-12-05 Cohn Michael B. Compliant hermetic package
US6703069B1 (en) * 2002-09-30 2004-03-09 Intel Corporation Under bump metallurgy for lead-tin bump over copper pad
US6897148B2 (en) 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US7316063B2 (en) * 2004-01-12 2008-01-08 Micron Technology, Inc. Methods of fabricating substrates including at least one conductive via
US7129567B2 (en) * 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7300857B2 (en) * 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
KR100633456B1 (ko) * 2004-11-24 2006-10-16 주식회사 유니테스트 깊게 파진 트렌치를 구비하는 프로브 카드 및 그 제조방법
KR100632552B1 (ko) * 2004-12-30 2006-10-11 삼성전기주식회사 내부 비아홀의 필 도금 구조 및 그 제조 방법
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
SE1050461A1 (sv) 2006-02-01 2010-05-10 Silex Microsystems Ab Metoder för tillverkning av en startsubstratskiva för halvledartillverkning, med skivgenomgående anslutningar
US7645701B2 (en) * 2007-05-21 2010-01-12 International Business Machines Corporation Silicon-on-insulator structures for through via in silicon carriers
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8611677B2 (en) 2008-11-19 2013-12-17 Intellectual Ventures Fund 83 Llc Method for event-based semantic classification
SE534510C2 (sv) 2008-11-19 2011-09-13 Silex Microsystems Ab Funktionell inkapsling
FR2945665A1 (fr) 2009-05-18 2010-11-19 Alchimer Procede de revetement d'un substrat semi-conducteur par electrodeposition.
US8531033B2 (en) * 2009-09-07 2013-09-10 Advanced Interconnect Materials, Llc Contact plug structure, semiconductor device, and method for forming contact plug
CN102598224A (zh) * 2009-11-09 2012-07-18 三菱瓦斯化学株式会社 硅通孔工艺中的硅基板背面蚀刻用蚀刻液及使用该蚀刻液的具有硅通孔的半导体芯片的制造方法
TWI517445B (zh) * 2010-02-12 2016-01-11 精材科技股份有限公司 發光二極體封裝、用於發光二極體封裝之高反射型次基板及其製造方法
JP2012064882A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置およびその製造方法
KR101732975B1 (ko) * 2010-12-03 2017-05-08 삼성전자주식회사 반도체 장치의 제조 방법
US20120153477A1 (en) * 2010-12-17 2012-06-21 Skyworks Solutions, Inc. Methods for metal plating and related devices
US8329575B2 (en) * 2010-12-22 2012-12-11 Applied Materials, Inc. Fabrication of through-silicon vias on silicon wafers
CN103890940B (zh) * 2011-10-28 2017-03-01 英特尔公司 包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构
JP2014013810A (ja) * 2012-07-04 2014-01-23 Seiko Epson Corp 基板、基板の製造方法、半導体装置、及び電子機器

Also Published As

Publication number Publication date
US9613863B2 (en) 2017-04-04
HK1213089A1 (zh) 2016-06-24
WO2014051511A2 (en) 2014-04-03
US20160172241A1 (en) 2016-06-16
EP2901475B1 (en) 2020-02-26
EP2901475A4 (en) 2016-05-04
SE538062C2 (sv) 2016-02-23
US20150255344A1 (en) 2015-09-10
US9514985B2 (en) 2016-12-06
EP2901475A2 (en) 2015-08-05
WO2014051511A3 (en) 2014-05-22

Similar Documents

Publication Publication Date Title
US9613863B2 (en) Method for forming electroless metal through via
KR101784997B1 (ko) 전기화학적 도금 방법들
CN110192283A (zh) 具有无金接触部的氮化物结构及形成这种结构的方法
JP2578193B2 (ja) 半導体素子の製造方法
JPS63205951A (ja) 安定な低抵抗コンタクト
JP2010517267A (ja) 基板貫通相互接続を形成する方法
JPH021981A (ja) 珪素半導体デバイスに電気相互接続部を形成する方法
US20150179567A1 (en) Using materials with different etch rates to fill trenches in semiconductor devices
JPH0590204A (ja) 半導体デバイスの製造方法
KR0137579B1 (ko) 반도체 소자의 플러그 형성방법
TWI729821B (zh) 製造互連結構的方法
US20040229460A1 (en) Surface treatment of metal interconnect lines
CN104900662B (zh) 半导体器件及其形成方法
US6657301B2 (en) Contact structure, method of forming the same, semiconductor device, and method of manufacturing the same
US7041585B2 (en) Process for producing an integrated electronic component
TWI467664B (zh) Semiconductor device manufacturing method and semiconductor device
KR100672726B1 (ko) 반도체 소자의 금속배선 형성방법
KR100253358B1 (ko) 반도체 소자의 금속배선 형성방법
KR960015493B1 (ko) 반도체 소자의 금속배선 연결용 비아콘택 형성방법
JPH0521377A (ja) 半導体装置の製造方法
JPH01217910A (ja) 半導体装置の製造方法
JP2002009146A (ja) 半導体集積回路装置の製造方法および半導体集積回路装置
KR20000046076A (ko) 반도체 소자의 구리 배선 형성 방법
TW579571B (en) Method for manufacturing copper damascene structure
CN112687611A (zh) 互连结构及其形成方法