RU2113034C1 - Полупроводниковое устройство, обладающее двухслойной силицидной структурой и способы его изготовления /варианты/ - Google Patents

Полупроводниковое устройство, обладающее двухслойной силицидной структурой и способы его изготовления /варианты/ Download PDF

Info

Publication number
RU2113034C1
RU2113034C1 RU93005343A RU93005343A RU2113034C1 RU 2113034 C1 RU2113034 C1 RU 2113034C1 RU 93005343 A RU93005343 A RU 93005343A RU 93005343 A RU93005343 A RU 93005343A RU 2113034 C1 RU2113034 C1 RU 2113034C1
Authority
RU
Russia
Prior art keywords
silicide
layer
temperature
metal
forming
Prior art date
Application number
RU93005343A
Other languages
English (en)
Russian (ru)
Other versions
RU93005343A (ru
Inventor
Паек Су-Хион
Сеог Чой Джин
Original Assignee
Самсунг Электроникс Ко., Лтд.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Самсунг Электроникс Ко., Лтд. filed Critical Самсунг Электроникс Ко., Лтд.
Publication of RU93005343A publication Critical patent/RU93005343A/ru
Application granted granted Critical
Publication of RU2113034C1 publication Critical patent/RU2113034C1/ru

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
RU93005343A 1992-05-30 1993-05-28 Полупроводниковое устройство, обладающее двухслойной силицидной структурой и способы его изготовления /варианты/ RU2113034C1 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019920009414A KR950003233B1 (ko) 1992-05-30 1992-05-30 이중층 실리사이드 구조를 갖는 반도체 장치 및 그 제조방법
KR9414/1992 1992-05-30

Publications (2)

Publication Number Publication Date
RU93005343A RU93005343A (ru) 1995-06-19
RU2113034C1 true RU2113034C1 (ru) 1998-06-10

Family

ID=19333972

Family Applications (1)

Application Number Title Priority Date Filing Date
RU93005343A RU2113034C1 (ru) 1992-05-30 1993-05-28 Полупроводниковое устройство, обладающее двухслойной силицидной структурой и способы его изготовления /варианты/

Country Status (6)

Country Link
US (1) US6774023B1 (enExample)
EP (1) EP0573241B1 (enExample)
JP (1) JP2503187B2 (enExample)
KR (1) KR950003233B1 (enExample)
CN (2) CN1034198C (enExample)
RU (1) RU2113034C1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2405228C2 (ru) * 2008-12-15 2010-11-27 Белорусский государственный университет Способ формирования силицидов металлов
RU2791268C1 (ru) * 2022-06-03 2023-03-07 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ формирования полевых транзисторов

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6156630A (en) * 1997-08-22 2000-12-05 Micron Technology, Inc. Titanium boride gate electrode and interconnect and methods regarding same
SE515783C2 (sv) * 1997-09-11 2001-10-08 Ericsson Telefon Ab L M Elektriska anordningar jämte förfarande för deras tillverkning
US7282443B2 (en) * 2003-06-26 2007-10-16 Micron Technology, Inc. Methods of forming metal silicide
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types
US7105440B2 (en) * 2005-01-13 2006-09-12 International Business Machines Corporation Self-forming metal silicide gate for CMOS devices
US20100052072A1 (en) * 2008-08-28 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dual gate structure on a same chip for high-k metal gate technology
US8652914B2 (en) 2011-03-03 2014-02-18 International Business Machines Corporation Two-step silicide formation
CN105541337B (zh) * 2015-12-25 2017-12-08 中国科学院上海硅酸盐研究所 一种多金属硅化物粉体及其制备方法
US9837357B1 (en) 2017-02-06 2017-12-05 International Business Machines Corporation Method to reduce variability in contact resistance
TW202429576A (zh) * 2023-01-05 2024-07-16 美商應用材料股份有限公司 藉由鉬與鈦的整合之觸點電阻降低

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
DE3326142A1 (de) * 1983-07-20 1985-01-31 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminiumlegierung bestehenden aeusseren kontaktleiterbahnebene
JP2522924B2 (ja) * 1986-11-19 1996-08-07 三洋電機株式会社 金属シリサイド膜の形成方法
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4974056A (en) * 1987-05-22 1990-11-27 International Business Machines Corporation Stacked metal silicide gate structure with barrier
JPS6417470A (en) * 1987-07-13 1989-01-20 Toshiba Corp Semiconductor device
JPS6417471A (en) * 1987-07-13 1989-01-20 Toshiba Corp Semiconductor device
JPH0234967A (ja) * 1988-07-25 1990-02-05 Sony Corp 半導体装置及び半導体装置の製造方法
JPH02262371A (ja) * 1989-04-03 1990-10-25 Toshiba Corp 半導体装置及びその製造方法
US5194405A (en) * 1989-07-06 1993-03-16 Sony Corporation Method of manufacturing a semiconductor device having a silicide layer
JP2616034B2 (ja) * 1989-08-23 1997-06-04 日本電気株式会社 半導体集積回路装置
US5203957A (en) * 1991-06-12 1993-04-20 Taiwan Semiconductor Manufacturing Company Contact sidewall tapering with argon sputtering

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2405228C2 (ru) * 2008-12-15 2010-11-27 Белорусский государственный университет Способ формирования силицидов металлов
RU2791268C1 (ru) * 2022-06-03 2023-03-07 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ формирования полевых транзисторов
RU2834220C1 (ru) * 2024-07-08 2025-02-04 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления полупроводникового прибора
RU2850163C1 (ru) * 2024-12-17 2025-11-05 Федеральное Государственное Бюджетное Образовательное Учреждение Высшего Образования "Чеченский Государственный Университет Имени Ахмата Абдулхамидовича Кадырова" Способ изготовления силицида тантала

Also Published As

Publication number Publication date
KR930024089A (ko) 1993-12-21
US6774023B1 (en) 2004-08-10
JPH0637092A (ja) 1994-02-10
CN1076866C (zh) 2001-12-26
EP0573241A3 (enExample) 1994-02-16
JP2503187B2 (ja) 1996-06-05
CN1081283A (zh) 1994-01-26
CN1034198C (zh) 1997-03-05
CN1121642A (zh) 1996-05-01
EP0573241A2 (en) 1993-12-08
EP0573241B1 (en) 2000-02-09
KR950003233B1 (ko) 1995-04-06

Similar Documents

Publication Publication Date Title
Saraswat et al. Properties of low-pressure CVD tungsten silicide for MOS VLSI interconnections
US5970370A (en) Manufacturing capping layer for the fabrication of cobalt salicide structures
JP3132750B2 (ja) 多層構造、半導体構造、半導体デバイスのコンデンサ、シリコン構造の酸化を防ぐ方法、及び、ドーパントの拡散を防ぐ方法
US6017789A (en) Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O5 dielectric layer with amorphous diffusion barrier layer
US5863393A (en) Low angle, low energy physical vapor deposition of alloys
KR0155587B1 (ko) 반도체 웨이퍼의 실리콘 층 위에 규화 티탄 층을 형성하는 방법
US5406123A (en) Single crystal titanium nitride epitaxial on silicon
EP0501561B1 (en) Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed
US6284316B1 (en) Chemical vapor deposition of titanium
US5828131A (en) Low temperature formation of low resistivity titanium silicide
KR930003243A (ko) (111) 결정방향을 가지는 질화티타늄 방벽층을 형성시키는 방법
KR19990072884A (ko) 다결정실리콘구조물의제조방법
JPH065667B2 (ja) ドーパントの外拡散を禁止する方法及び半導体装置
RU2113034C1 (ru) Полупроводниковое устройство, обладающее двухслойной силицидной структурой и способы его изготовления /варианты/
JP2002026288A (ja) １トランジスタメモリ用のｍｏｃｖｄ金属酸化物
US5138432A (en) Selective deposition of tungsten on TiSi2
US5286678A (en) Single step salicidation process
US6831362B2 (en) Diffusion barrier layer for semiconductor device and fabrication method thereof
US4526665A (en) Method of depositing fully reacted titanium disilicide thin films
US4954852A (en) Sputtered metallic silicide gate for GaAs integrated circuits
EP0100454B1 (en) Semiconductor device having a conductive layer consisting of a high-melting point metal silicide and a method for manufacturing such a semiconductor device
JPH04280669A (ja) 多結晶シリコン膜の形成方法
JP2542617B2 (ja) 半導体装置の製造方法
JPH04252018A (ja) 多結晶シリコン膜の形成方法
KR100264029B1 (ko) 티타늄 실리사이드막을 가진 반도체 장치 제조 방법