CN1121642A - 具双层硅化物结构的半导体器件制造方法 - Google Patents
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 238000000137 annealing Methods 0.000 claims abstract 3
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 229910052715 tantalum Inorganic materials 0.000 claims description 17
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 4
- 230000004927 fusion Effects 0.000 claims 4
- 229910052750 molybdenum Inorganic materials 0.000 claims 4
- 239000011733 molybdenum Substances 0.000 claims 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 4
- 229910052721 tungsten Inorganic materials 0.000 claims 4
- 239000010937 tungsten Substances 0.000 claims 4
- 230000005669 field effect Effects 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 1
- 239000002904 solvent Substances 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 31
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000005054 agglomeration Methods 0.000 abstract 1
- 230000002776 aggregation Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 7
- 239000000428 dust Substances 0.000 description 6
- 238000007669 thermal treatment Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical class F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 3
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 238000005979 thermal decomposition reaction Methods 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 241001076960 Argon Species 0.000 description 2
- 235000013876 argon Nutrition 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005354 coacervation Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241000287828 Gallus gallus Species 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种具双层硅化物结构的半导体器件及其制造方法在后续的热处理过程中均质地保持硅化钛表面以改进硅化钛在高温下的稳定性。双层硅化物是多晶硅上淀积硅化物形成温度为预定的第一温度的金属形成第一金属硅化物层,并淀积硅化物形成温度为低于第一温度的第二温度的金属形成第二金属硅化物层,从而大大改善了由硅化钛构成的传统半导体器件在后续的热处理过程中出现的不稳定性,避免了晶粒生长型性变形和凝聚等现象。
Description
本发明涉及一种MOS(金属氧化物半导体)存储器,更具体地说,涉及硅化钛的高温稳定性有所改善的一种半导体器件,而硅化钛在DRAM(动态随机存储器)中是用作多晶硅化物(polycide)的选通线的。
在半导体器件中,通常是利用如硅化钛之类的高熔点金属硅化物设计出电阻低的内部布线材料的。
硅化钛是将高熔点金属的钛(Ti)与硅(Si)结合起来制取的。硅化钛的导电性能优异,耐热性能突出,因此硅化钛有利于进行微结构处理,因而适宜用作高集成度的半导体存储器件。硅化钛电阻低,所以广泛应用于自对准硅化物(SALICIDE)(参看1990年12月的IEDM 9-12期,第249-252页)。
图1A、1B和1C举例说明了按传统的方法制造硅化钛的一个例子。在图1A所示的工序中,在大约920℃温度下通过氧化在比电阻约为5-25欧厘米的单晶硅衬底1上生长出厚约1,000埃的二氧化硅(SiO)层2。然后,在250毫乇大气、大约625℃温度下通过低压化学汽相淀积法(LPCVD)使硅烷(SiH4)热分解,从而在二氧化硅层2的上部分淀积出厚约2,500埃的多晶硅层3。淀积出多晶硅层3之后,用离子注入法将磷(P)注入多晶硅层3中。这时,离子注入能量约为30千电子伏特,注入剂量约有5×1015离子/平方厘米。为避免多晶硅层3的表面因离子注入而损伤,在大约900℃下在炉中进行热处理30分钟。热处理完毕之后,用溅射法在多晶硅3的上部分淀积厚约400-600埃的钛,再对得出的结构在大约800℃的氩(Ar)气氛中进行快速热处理,历时约20秒钟。快速热处理使多晶硅3与钛4相互进行反应,从而形成硅化钛5,如图1B中所示。
硅化钛的熔点约为1540℃,即换算成绝对温度为1813°K,而在814℃下硅化钛开始出现高温不稳定性,这个温度为该绝对温度的0.6倍。本技术领域的行家们都知道,高熔点金属硅化物开始出现不稳定的既定温度是通过其熔点的绝对温度乘以0.6求出的。硅化钛的熔点随其处理条件的不同略有变异,但硅化钛通常是在900℃开始出现不稳定。
因此,在以后900℃或更高的温度下进行的热处理的过程中,硅化钛中的晶粒生长,而且产生塑性变形。与此同时,由于硅外延生长,均质薄膜中产生凝聚现象,从而使薄膜不连续,形成半岛状的微结构。
换句话说,如图IC的结构6中所示,硅化钛成了呈半岛状的不连续薄膜,从而使多晶硅3的表面露出来。由于硅化钛的结构不连续,内部布线的电阻显著增加。上面说过,布线的电阻增加对半导存储器件的工作特性有不利的影响,同时降低工作的可靠性。
因此,本发明的目的是提供一种在以后的高温热处理过程中能匀质维持硅化钛的表面的计导体器件及其制造方法。
本发明的另一个目的是提供一种供改善硅化钛因传统方法所引起的高温不稳定性的半导体器件及其制造方法。
为达到本发明的上述目的,本发明提供一种具双层硅化物结构的半导体器件,该器件包括:单晶结构预定的硅衬底;氧化物层,形成在单晶硅衬底的整个表面上;多晶硅层,生长在氧化物层的整个表面上;第一金属硅化物层,通过在多晶硅层的上部分淀积金属而形成,该金属硅化物形成温度为预定的第一温度;和第二金属硅化物层,通过在硅化物形成温度为第一温度的金属的上部分淀积另一金属而形成,该另一金属硅化物形成温度为低于第一温度的第二温度。
为达到本发明的另一个目的,本发明提供制造具双层硅化物结构的半导体器件的一种方法,该方法包括下列步骤:在单晶硅衬底的整个表面形成一层氧化物层;在氧化物层的整个表面上生长出一层多晶硅层;在多晶硅层的上部分淀积上硅化物形成温度为预定的第一温度的金属,由此形成第一金属硅化物层;在硅化物形成温度为第一温度的金属的上部分淀积上硅化物形成温度为低于第一温度的第二温度的金属,由此形成第二金属硅化物层。
参看附图详细说明本发明的一个实施例,由此可以更清楚地了解本发明的上述目的和其它好处。附图中:
图1A至IC展示用传统方法制造半导体器件过程的剖视图;
图2A和2展示本发明半导体器件制造过程一个实施例的剖视图;
图3A和3B展示本发明半导体器件制造过程另一个实施例的剖视图;
图4是传统方法和本发明的半导体器件在薄层电阻方面的比较表。
图2A和2B示出了本发明双层硅化物制造过程的一个实施例。
图2A中,在920℃比电阻约为5-25欧厘米的单晶硅衬底7上通过热氧化生长出厚约1000埃的二氧化硅(SiO2)层8。在大约625℃和250毫乇大气下通过低压化学汽相淀积法(LPCVD)热分解硅烷(SiH4),从而在二氧化硅层8的上部分淀积出厚2,500埃的多晶硅层9之后,通过离子注入法往多晶硅层9中注入磷(P)。这时,离子注入能量约30千电伏特,离子注入剂量约5×1015离子/平方厘米。为防止多晶硅层9的表面因离子注入而损伤,用经稀释的lF溶液进行腐蚀,该HF溶液是将氟化氢(HF)按1∶100的比例溶解在水中制取的。腐蚀之后,用溅射法在多晶硅层9的上部分淀积上厚约100-200埃的钽10,再用溅射法在钽10上淀积上厚约400-600埃的钛11。钛11淀积完毕之后,在800℃的氩(Ar)气氛中对所得出的结构进行快速热处理,历时20秒钟。通过此快速热处理,如图2B所示,多晶硅9与钽10反应从而形成硅化钽(TaSi2)12,同时多晶硅9与钛11反应从而形成钛(TiSi2)13。
图3A和3B示出了本发明双层硅化物制造过程的另一个实施例。
图3A中,在920℃比电阻约为5-25欧厘来的单晶硅衬底14上通过热氧化生长出厚约1000埃的二氧化硅(SiO2)层15。通过LPCVD在625℃和约250毫乇大气下热分解硅烷SiH4,从而在二氧化硅层15的上部分淀积上厚约2,500埃的多晶硅层16之后,用离子注入法往多晶硅层16中注入磷(P)。这时,离子注入能量约为30千电子伏特,离子注入剂量鸡为5×1015离子/平立厘米。为避免多晶硅层16的表面因离子注入而损伤,用经稀释的HF溶液进行腐蚀,该HF溶液是将氟化氢(HF)以1∶100的比例溶解入水中制取的。图3B中,腐蚀完毕时,用溅射法采用由硅化钽组成的复合靶在多晶硅层16上部分淀积厚约200-400埃的硅化钽17,再用溅射法采用由硅化钛构成的复合靶在硅化钽17上淀积存约800-1200埃的硅化钛18。硅化钛18淀积完毕之后,在800℃的氩(Ar)气氛中对所得出的结构进行快速热处理,历时20秒钟。这个快速热处理使非晶态的双层硅化物具图3B所示的晶体结构。
硅化钽的溶点为2,200℃,即换算成绝对温度为2,473°K。该绝对温度的0.6倍为1483.8°K,而硅化钽在1210.8℃开始出现高温不稳定性,这个温度比硅化钛开始不稳定的814℃高得多。由硅化钽和硅化钛构成的双层硅化构结构,即使以后的热处理是在900℃或更高的温度下进行,也可避免传统方法中出现的晶粒生长、塑性变形和凝聚等现象。
我们测定了本发明由硅化钽和硅化钛构成的双层硅化物结构的高温稳定性并将其与传统方法的硅化钛加以比较,结果如图4所示。图4的表是在氮(N2)气氛中和分别在850℃、900℃、950℃和1000℃下对本发明的双层硅化物和传统方法的硅化物层进行30分钟热处理之后编制的。从图4中可以看出,在传统方法中,硅化钛在950℃下开始凝聚、从而薄层电阻大大提高了。更详细地说,薄层电阻在850℃下为2.2欧/平方,但在950℃下为5.3欧/平方,即增加了两倍。另外,在1000℃下的薄层电阻非常高,达2940欧/平方。但在钽和钛的双层硅化物结构中,可以看到薄层电阻的升幅微不足道,在1000℃下的薄层电阻为5.3欧/平方,相比之下,在850℃下的薄层电阻为3.8欧/平方。
虽然本发明的一个实施例中采用硅化钽作为下面的硅化物层,但在本发明的另一个实施例中可以采用硅化钼、硅化钨等作为下面的硅化物层,其熔点比用作上面的硅化物层的硅化钛高。
硅化钨和硅化钼的熔点分别为2165℃和1980℃,换算成绝对温度分别为2438°K和2253°K。这些绝对温度的0.6倍为1462.8°K和1351.8°K。因此硅化钨在1189.8℃开始出现高温不稳定性,硅化钼在1078.8℃开始出现高温不稳定性。
这些温度都双硅化钛因温度开始出现不稳定性的814℃高得多。因此在900℃或更高温度下进行的后处理过程中可以防止凝聚现象。
如上所述,由于本发明具双层硅化物的半导体器件大大改善了在以后的热处理中出现的高温不稳定性,因而避免了晶粒生长、塑性变形和凝聚等现象,从而改善了半导体器件的工作特性。
虽然本发明特别是就本发明的一些特殊实施例进行展示和说明的,但本技术领域的行家们都知道,在不脱离本说明书所附权利要求书中所述的本发明范围的前提下是可以对这些实施例的形式和细节进行种种修改的。
Claims (14)
1.一种在多晶硅层表面上带有预定薄层电阻的第一金属硅化物连续层的制造方法,该多晶硅层形成在氧化物层上,而氧化物形成在单晶硅衬底上,当制造半导体器件上的导体有别于金属氧化物半导体场效应晶体管的栅电极时,所述第一金属硅化物只有在超过0.6倍的所述第一金属硅化物溶解的绝对温度下才呈现高温不稳定性,所述方法包括下列顺序步骤:
在所述单晶硅衬底上形成所述氧化层;
在所述氧化层上形成所述多晶硅层;
淀积一层第二金属,所述第二金属能够形成第二金属硅化物,使其只在超过0.6倍的所述第二金属硅化物熔解的绝对温度下才呈现高温不稳定性,所述第二金属这样选择,使得在由所述第二金属硅化物呈现出高温不稳定性的温度高于所述半导体器件在制造或随后的工作期间应经历的温度;
在第二金属的所述层上淀积一层所述第一金属;
迅速将上述步骤所得结构退火,以使所述第一金属和所述多晶硅层起反应,结果形成所述第一金属硅化物层,并使所述第二金属和所述多晶硅层起反应,结果形成一层所述第二金属硅化物层;以及
此后有意识地使从所述退火得到的结构处在高于所述第一金属硅化物熔解的绝对温度的0.6倍的高温、但低于所述第二金属硅化物熔解的绝对温度下几分钟,由于所述高温,所述第二金属硅化物抢先在所述第一金属硅化物层出现断续性,如果所述第一金属硅化物直接毗连所述多晶硅层就会出现这种断续性,而且会使所述薄层电阻不合乎需要地提升到高于所述预定值。
2.如权利要求1的方法,其中所述第一金属是钛,而所述高温至少是950℃。
3.如权利要求2的方法,其中所述钛淀积的原度范围约400-600。
4.如权利要求3的方法,其中所述第二金属选自钽、钼和钨的组合。
5.如权利要求4的方法,其中所述第二金属淀积的厚度范围为100-200 。
6.如权利要求2的方法,其中所述第二金属选自钽、钼和钨的组合。
7.如权利要求6的方法,其中所述第二金属淀积的厚度范围约为100-200。
8.一种在多晶硅层表面上带有预定薄层电阻的第一金属硅化物连续层的制造方法,该多晶硅层形成在氧化物层上,而氧化物形成在单晶硅衬底上,当制造半导体器件上的导体有别于金属氧化物半导体场效应晶体管的栅电极时,所述第一金属硅化物只有在超过0.6倍的所述第一金属硅化物溶解的绝对温度下才量现高温不稳定性,所述方法包括下列顺序步骤:
在所述单晶硅衬底上形成所述氧化层;
在所述氧化层上形成所述多晶硅层;
采用由所述第二金属硅化物组成的复合靶在所述多晶硅层上溅射第二金属硅化物的连续层,硅和一具有第二硅化物形成温度的第二金属是所述第二金属硅化物的基本组分,所述第二硅化物形温度高于所述第一硅化物形成温度;
用所述第一金属硅化物组成的复合靶在所说第二金属硅化物层上溅射所述第一金属硅化物层;以及
之后有意识地使从所述第一金属硅化物层的所述溅射得到的结构在高于0.6倍的所述第一金属硅化物熔解的绝对温度但低于0.6倍的所述第二金属硅化物熔解的绝对温度下经历至少几分钟,由于所述高温,所述第二金属硅化物层抢先在所述第一金属硅化物层中出现继续性,如果所述第一金属硅化物直接毗连所述多晶硅层就会出现这种断续性,而且会使所述薄层电阻不合乎需要地提升到超出所述预定值。
9.如权利要求8的方法,其中所述第一金属是钛,而所述高温至少是950℃。
10.如权利要求9的方法,其中所述钛淀积的厚度范围约400-600。
11.如权利要求10的方法,其中所述第二金属选自钽、钼和钨的组合。
12.如权利要求11的方法,其中所述第二金属淀积的厚度范围约为100-200。
13.如权利要求9的方法,其中所述第二金属选自钽、钼和钨的组合。
14.如权利要求13的方法,其中所述第二金属淀积淀积的厚度范围约为100-200。
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CN95109584A Expired - Lifetime CN1076866C (zh) | 1992-05-30 | 1995-10-31 | 在多晶硅层表面上的高熔点金属硅化物层的制造方法 |
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Country Status (6)
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US6156630A (en) * | 1997-08-22 | 2000-12-05 | Micron Technology, Inc. | Titanium boride gate electrode and interconnect and methods regarding same |
US7282443B2 (en) * | 2003-06-26 | 2007-10-16 | Micron Technology, Inc. | Methods of forming metal silicide |
US7112483B2 (en) * | 2003-08-29 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a device having multiple silicide types |
US7105440B2 (en) * | 2005-01-13 | 2006-09-12 | International Business Machines Corporation | Self-forming metal silicide gate for CMOS devices |
US20100052072A1 (en) * | 2008-08-28 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual gate structure on a same chip for high-k metal gate technology |
US8652914B2 (en) | 2011-03-03 | 2014-02-18 | International Business Machines Corporation | Two-step silicide formation |
CN105541337B (zh) * | 2015-12-25 | 2017-12-08 | 中国科学院上海硅酸盐研究所 | 一种多金属硅化物粉体及其制备方法 |
US9837357B1 (en) | 2017-02-06 | 2017-12-05 | International Business Machines Corporation | Method to reduce variability in contact resistance |
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JPH0234967A (ja) * | 1988-07-25 | 1990-02-05 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
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KR950003233B1 (ko) | 1995-04-06 |
EP0573241B1 (en) | 2000-02-09 |
CN1076866C (zh) | 2001-12-26 |
EP0573241A2 (en) | 1993-12-08 |
JP2503187B2 (ja) | 1996-06-05 |
CN1034198C (zh) | 1997-03-05 |
RU2113034C1 (ru) | 1998-06-10 |
CN1081283A (zh) | 1994-01-26 |
US6774023B1 (en) | 2004-08-10 |
JPH0637092A (ja) | 1994-02-10 |
KR930024089A (ko) | 1993-12-21 |
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