NO20022134L - Metalldistribusjonslag som har loddbare og trådbindingsbare kontaktflater - Google Patents
Metalldistribusjonslag som har loddbare og trådbindingsbare kontaktflaterInfo
- Publication number
- NO20022134L NO20022134L NO20022134A NO20022134A NO20022134L NO 20022134 L NO20022134 L NO 20022134L NO 20022134 A NO20022134 A NO 20022134A NO 20022134 A NO20022134 A NO 20022134A NO 20022134 L NO20022134 L NO 20022134L
- Authority
- NO
- Norway
- Prior art keywords
- solderable
- contact surfaces
- distribution layer
- metal distribution
- wire bondable
- Prior art date
Links
- 239000002184 metal Substances 0.000 title 1
Classifications
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
- Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
- Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/4921—Contact or terminal manufacturing by assembling plural parts with bonding
- Y10T29/49211—Contact or terminal manufacturing by assembling plural parts with bonding of fused material
- Y10T29/49213—Metal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/434,711 US6511901B1 (en) | 1999-11-05 | 1999-11-05 | Metal redistribution layer having solderable pads and wire bondable pads |
PCT/US2000/024087 WO2001035462A1 (en) | 1999-11-05 | 2000-08-31 | Metal redistribution layer having solderable pads and wire bondable pads |
Publications (2)
Publication Number | Publication Date |
---|---|
NO20022134D0 NO20022134D0 (no) | 2002-05-03 |
NO20022134L true NO20022134L (no) | 2002-05-03 |
Family
ID=23725346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO20022134A NO20022134L (no) | 1999-11-05 | 2002-05-03 | Metalldistribusjonslag som har loddbare og trådbindingsbare kontaktflater |
Country Status (10)
Country | Link |
---|---|
US (3) | US6511901B1 (no) |
EP (1) | EP1228530A1 (no) |
JP (1) | JP2003514380A (no) |
KR (1) | KR100643065B1 (no) |
CN (1) | CN1198337C (no) |
CA (1) | CA2388926A1 (no) |
HK (1) | HK1049913B (no) |
NO (1) | NO20022134L (no) |
TW (1) | TW477051B (no) |
WO (1) | WO2001035462A1 (no) |
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JP5986499B2 (ja) | 2012-12-21 | 2016-09-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
TWI489569B (zh) * | 2013-02-08 | 2015-06-21 | 矽品精密工業股份有限公司 | 半導體封裝結構之構件製法 |
US10028380B2 (en) * | 2014-10-22 | 2018-07-17 | Sandisk Technologies Llc | Semiconductor package with dual second level electrical interconnections |
KR102357937B1 (ko) * | 2015-08-26 | 2022-02-04 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
KR102372349B1 (ko) | 2015-08-26 | 2022-03-11 | 삼성전자주식회사 | 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지 |
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-
1999
- 1999-11-05 US US09/434,711 patent/US6511901B1/en not_active Expired - Fee Related
-
2000
- 2000-08-31 EP EP00961480A patent/EP1228530A1/en not_active Withdrawn
- 2000-08-31 WO PCT/US2000/024087 patent/WO2001035462A1/en active Application Filing
- 2000-08-31 KR KR1020027005741A patent/KR100643065B1/ko not_active IP Right Cessation
- 2000-08-31 JP JP2001537102A patent/JP2003514380A/ja not_active Withdrawn
- 2000-08-31 CN CNB00815449XA patent/CN1198337C/zh not_active Expired - Fee Related
- 2000-08-31 CA CA002388926A patent/CA2388926A1/en not_active Abandoned
- 2000-10-12 TW TW089121290A patent/TW477051B/zh not_active IP Right Cessation
-
2001
- 2001-08-30 US US09/944,347 patent/US6577008B2/en not_active Expired - Lifetime
-
2002
- 2002-05-03 NO NO20022134A patent/NO20022134L/no not_active Application Discontinuation
-
2003
- 2003-01-27 US US10/352,632 patent/US6762117B2/en not_active Expired - Fee Related
- 2003-03-14 HK HK03101891.5A patent/HK1049913B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1387681A (zh) | 2002-12-25 |
KR20020044590A (ko) | 2002-06-15 |
HK1049913A1 (en) | 2003-05-30 |
WO2001035462A1 (en) | 2001-05-17 |
US6762117B2 (en) | 2004-07-13 |
JP2003514380A (ja) | 2003-04-15 |
NO20022134D0 (no) | 2002-05-03 |
US20030119297A1 (en) | 2003-06-26 |
TW477051B (en) | 2002-02-21 |
US20020025585A1 (en) | 2002-02-28 |
CA2388926A1 (en) | 2001-05-17 |
US6511901B1 (en) | 2003-01-28 |
US6577008B2 (en) | 2003-06-10 |
CN1198337C (zh) | 2005-04-20 |
KR100643065B1 (ko) | 2006-11-10 |
EP1228530A1 (en) | 2002-08-07 |
HK1049913B (zh) | 2005-08-05 |
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