NL1011933C2 - Werkwijze voor het vormen van contactproppen onder gelijktijdig vlak maken van het substraatoppervlak in ge´ntegreerde schakelingen. - Google Patents

Werkwijze voor het vormen van contactproppen onder gelijktijdig vlak maken van het substraatoppervlak in ge´ntegreerde schakelingen. Download PDF

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Publication number
NL1011933C2
NL1011933C2 NL1011933A NL1011933A NL1011933C2 NL 1011933 C2 NL1011933 C2 NL 1011933C2 NL 1011933 A NL1011933 A NL 1011933A NL 1011933 A NL1011933 A NL 1011933A NL 1011933 C2 NL1011933 C2 NL 1011933C2
Authority
NL
Netherlands
Prior art keywords
insulating layer
forming
layer
contact hole
conductive
Prior art date
Application number
NL1011933A
Other languages
English (en)
Dutch (nl)
Other versions
NL1011933A1 (nl
Inventor
Bo-Un Yoon
Seok-Ji Hong
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL1011933A1 publication Critical patent/NL1011933A1/xx
Application granted granted Critical
Publication of NL1011933C2 publication Critical patent/NL1011933C2/nl

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
NL1011933A 1998-05-07 1999-04-29 Werkwijze voor het vormen van contactproppen onder gelijktijdig vlak maken van het substraatoppervlak in ge´ntegreerde schakelingen. NL1011933C2 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019980016333A KR100268459B1 (ko) 1998-05-07 1998-05-07 반도체 장치의 콘택 플러그 형성 방법
KR19980016333 1998-05-07

Publications (2)

Publication Number Publication Date
NL1011933A1 NL1011933A1 (nl) 1999-11-09
NL1011933C2 true NL1011933C2 (nl) 2002-09-24

Family

ID=19537111

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1011933A NL1011933C2 (nl) 1998-05-07 1999-04-29 Werkwijze voor het vormen van contactproppen onder gelijktijdig vlak maken van het substraatoppervlak in ge´ntegreerde schakelingen.

Country Status (9)

Country Link
US (1) US6218291B1 (ko)
JP (1) JP4031148B2 (ko)
KR (1) KR100268459B1 (ko)
CN (1) CN1114942C (ko)
DE (1) DE19920970C2 (ko)
FR (1) FR2782841B1 (ko)
GB (1) GB2337161B (ko)
NL (1) NL1011933C2 (ko)
TW (1) TW444373B (ko)

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KR100474537B1 (ko) * 2002-07-16 2005-03-10 주식회사 하이닉스반도체 산화막용 ｃｍｐ 슬러리 조성물 및 이를 이용한 반도체소자의 제조 방법
US6818555B2 (en) * 2002-10-07 2004-11-16 Taiwan Semiconductor Manufacturing Co., Ltd Method for metal etchback with self aligned etching mask
JP4679277B2 (ja) * 2005-07-11 2011-04-27 富士通セミコンダクター株式会社 半導体装置の製造方法
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US9716035B2 (en) * 2014-06-20 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Combination interconnect structure and methods of forming same
CN105336676B (zh) * 2014-07-29 2018-07-10 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法
WO2018031926A1 (en) * 2016-08-11 2018-02-15 Tokyo Electron Limited Method for etch-based planarization of a substrate

Citations (8)

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US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
EP0478871A1 (en) * 1990-10-01 1992-04-08 STMicroelectronics S.r.l. Formation of contact plugs by blanket CVD deposition and etchback
US5306947A (en) * 1992-01-16 1994-04-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
JPH07106419A (ja) * 1993-10-05 1995-04-21 Toshiba Corp 半導体装置の製造方法
US5496774A (en) * 1993-12-01 1996-03-05 Vlsi Technology, Inc. Method improving integrated circuit planarization during etchback
JPH08236524A (ja) * 1995-02-28 1996-09-13 Nec Corp 半導体装置の製造方法
JPH10189603A (ja) * 1996-12-20 1998-07-21 Samsung Electron Co Ltd 半導体素子のコンタクトプラグ形成方法
FR2764734A1 (fr) * 1997-06-11 1998-12-18 Samsung Electronics Co Ltd Procede de formation de plots de contact d'un dispositif a semiconducteur

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US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
JPH01108746A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置の製造方法
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
JP3216104B2 (ja) * 1991-05-29 2001-10-09 ソニー株式会社 メタルプラグ形成方法及び配線形成方法
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
JP2756887B2 (ja) * 1992-03-02 1998-05-25 三菱電機株式会社 半導体装置の導電層接続構造およびその製造方法
US5250472A (en) * 1992-09-03 1993-10-05 Industrial Technology Research Institute Spin-on-glass integration planarization having siloxane partial etchback and silicate processes
US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP
US5268330A (en) * 1992-12-11 1993-12-07 International Business Machines Corporation Process for improving sheet resistance of an integrated circuit device gate
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface
JP3326698B2 (ja) * 1993-03-19 2002-09-24 富士通株式会社 集積回路装置の製造方法
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US5786273A (en) * 1995-02-15 1998-07-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and associated fabrication method
US5527736A (en) * 1995-04-03 1996-06-18 Taiwan Semiconductor Manufacturing Co. Dimple-free tungsten etching back process
US5747383A (en) * 1995-09-05 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd Method for forming conductive lines and stacked vias
US5665657A (en) * 1995-09-18 1997-09-09 Taiwan Semiconductor Manufacturing Company, Ltd Spin-on-glass partial etchback planarization process
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric
US5861342A (en) * 1995-12-26 1999-01-19 Vlsi Technology, Inc. Optimized structures for dummy fill mask design
US5830804A (en) * 1996-06-28 1998-11-03 Cypress Semiconductor Corp. Encapsulated dielectric and method of fabrication
US6025269A (en) * 1996-10-15 2000-02-15 Micron Technology, Inc. Method for depositioning a substantially void-free aluminum film over a refractory metal nitride layer
US5961617A (en) * 1997-08-18 1999-10-05 Vadem System and technique for reducing power consumed by a data transfer operations during periods of update inactivity

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
EP0478871A1 (en) * 1990-10-01 1992-04-08 STMicroelectronics S.r.l. Formation of contact plugs by blanket CVD deposition and etchback
US5306947A (en) * 1992-01-16 1994-04-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
JPH07106419A (ja) * 1993-10-05 1995-04-21 Toshiba Corp 半導体装置の製造方法
US5496774A (en) * 1993-12-01 1996-03-05 Vlsi Technology, Inc. Method improving integrated circuit planarization during etchback
JPH08236524A (ja) * 1995-02-28 1996-09-13 Nec Corp 半導体装置の製造方法
JPH10189603A (ja) * 1996-12-20 1998-07-21 Samsung Electron Co Ltd 半導体素子のコンタクトプラグ形成方法
US5960310A (en) * 1996-12-20 1999-09-28 Samsung Electronics Co., Ltd. Polishing methods for forming a contact plug
FR2764734A1 (fr) * 1997-06-11 1998-12-18 Samsung Electronics Co Ltd Procede de formation de plots de contact d'un dispositif a semiconducteur

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PATENT ABSTRACTS OF JAPAN vol. 1995, no. 07 31 August 1995 (1995-08-31) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 01 31 January 1997 (1997-01-31) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 12 31 October 1998 (1998-10-31) *

Also Published As

Publication number Publication date
DE19920970A1 (de) 1999-11-18
GB2337161B (en) 2000-11-08
CN1235373A (zh) 1999-11-17
KR19990084516A (ko) 1999-12-06
FR2782841B1 (fr) 2003-08-29
US6218291B1 (en) 2001-04-17
JP4031148B2 (ja) 2008-01-09
GB9909486D0 (en) 1999-06-23
NL1011933A1 (nl) 1999-11-09
CN1114942C (zh) 2003-07-16
DE19920970C2 (de) 2002-10-24
GB2337161A (en) 1999-11-10
JP2000003915A (ja) 2000-01-07
TW444373B (en) 2001-07-01
KR100268459B1 (ko) 2000-10-16
FR2782841A1 (fr) 2000-03-03

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Effective date: 20020723

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VD1 Lapsed due to non-payment of the annual fee

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