MX170835B - Circuito habilitado de escritura cache retardada para un sistema de microcomputadora de doble bus con un 80386 y 82385 - Google Patents

Circuito habilitado de escritura cache retardada para un sistema de microcomputadora de doble bus con un 80386 y 82385

Info

Publication number
MX170835B
MX170835B MX016169A MX1616989A MX170835B MX 170835 B MX170835 B MX 170835B MX 016169 A MX016169 A MX 016169A MX 1616989 A MX1616989 A MX 1616989A MX 170835 B MX170835 B MX 170835B
Authority
MX
Mexico
Prior art keywords
cache
write
enabler
microcomputer system
input
Prior art date
Application number
MX016169A
Other languages
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX170835B publication Critical patent/MX170835B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Hardware Redundancy (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
  • Saccharide Compounds (AREA)
  • Multi Processors (AREA)

Abstract

La presente invención se refiere a un sistema de microcomputadora de bus múltiple abarcando: un procesador 80386 y un subsistema caché conectados juntos por un bus local del CPU, dicho subsistema caché comprendiendo un controlador caché 82385 y una memoria caché y elementos lógicos conectando señales del habilitador de escritura de dicho controlador caché 82385 a dicha memoria caché, abarcando dichos medios lógicos: a) elementos lógicos de retardo sensibles a la condición de escritura caché causada por una lectura no hallada y sensibles a la entrada del habilitador de escritura de dicho controlador caché 82385 y teniendo una terminal de habilitador de escritura para producir una señal retardada de habilitador de escritura en dicha terminal de habilitador de escritura, b) una puerta lógica con una primera entrada acoplada a dicha salida de habilitador de escritura de dicho controlador caché 82385 y una segunda entrada acoplada a dicha terminal de habilitador de escritura, y una salida acoplada a una entrada de habilitador de escritura de dicha memoria caché.
MX016169A 1988-05-26 1989-05-24 Circuito habilitado de escritura cache retardada para un sistema de microcomputadora de doble bus con un 80386 y 82385 MX170835B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,890 US5175826A (en) 1988-05-26 1988-05-26 Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385

Publications (1)

Publication Number Publication Date
MX170835B true MX170835B (es) 1993-09-20

Family

ID=22735299

Family Applications (1)

Application Number Title Priority Date Filing Date
MX016169A MX170835B (es) 1988-05-26 1989-05-24 Circuito habilitado de escritura cache retardada para un sistema de microcomputadora de doble bus con un 80386 y 82385

Country Status (25)

Country Link
US (1) US5175826A (es)
EP (1) EP0343989B1 (es)
JP (1) JP2755330B2 (es)
KR (1) KR930001584B1 (es)
CN (1) CN1019151B (es)
AT (1) ATE128566T1 (es)
AU (1) AU615542B2 (es)
BE (1) BE1002653A4 (es)
BR (1) BR8902383A (es)
CA (1) CA1314103C (es)
CO (1) CO4520299A1 (es)
DE (2) DE3911721A1 (es)
DK (1) DK170677B1 (es)
ES (1) ES2078237T3 (es)
FI (1) FI96244C (es)
FR (1) FR2632092A1 (es)
GB (2) GB8904920D0 (es)
HK (1) HK11592A (es)
IT (1) IT1230208B (es)
MX (1) MX170835B (es)
MY (1) MY106968A (es)
NL (1) NL8901327A (es)
NO (1) NO175837C (es)
SE (1) SE8901308L (es)
SG (1) SG110991G (es)

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US5586302A (en) * 1991-06-06 1996-12-17 International Business Machines Corporation Personal computer system having storage controller with memory write control
US5361368A (en) * 1991-09-05 1994-11-01 International Business Machines Corporation Cross interrogate synchronization mechanism including logic means and delay register
US5802548A (en) * 1991-10-25 1998-09-01 Chips And Technologies, Inc. Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers
US5333276A (en) * 1991-12-27 1994-07-26 Intel Corporation Method and apparatus for priority selection of commands
US5426739A (en) * 1992-03-16 1995-06-20 Opti, Inc. Local bus - I/O Bus Computer Architecture
US5309568A (en) * 1992-03-16 1994-05-03 Opti, Inc. Local bus design
US5471585A (en) * 1992-09-17 1995-11-28 International Business Machines Corp. Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports
US5898894A (en) * 1992-09-29 1999-04-27 Intel Corporation CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval
US6487626B2 (en) 1992-09-29 2002-11-26 Intel Corporaiton Method and apparatus of bus interface for a processor
US5613153A (en) * 1994-10-03 1997-03-18 International Business Machines Corporation Coherency and synchronization mechanisms for I/O channel controllers in a data processing system
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US6397295B1 (en) 1999-01-04 2002-05-28 Emc Corporation Cache mechanism for shared resources in a multibus data processing system
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
JP2005221731A (ja) * 2004-02-05 2005-08-18 Konica Minolta Photo Imaging Inc 撮像装置
US8996833B2 (en) * 2013-03-11 2015-03-31 Intel Corporation Multi latency configurable cache

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US4190885A (en) * 1977-12-22 1980-02-26 Honeywell Information Systems Inc. Out of store indicator for a cache store in test mode
US4171538A (en) * 1978-01-23 1979-10-16 Rockwell International Corporation Elastic store slip circuit apparatus for preventing read and write operations interference
US4189770A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Cache bypass control for operand fetches
JPS58169958A (ja) * 1982-03-31 1983-10-06 Fujitsu Ltd Ｍｉｓスタテイツク・ランダムアクセスメモリ
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
US4513372A (en) * 1982-11-15 1985-04-23 Data General Corporation Universal memory
US4686621A (en) * 1983-06-30 1987-08-11 Honeywell Information Systems Inc. Test apparatus for testing a multilevel cache system with graceful degradation capability
JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
US4736293A (en) * 1984-04-11 1988-04-05 American Telephone And Telegraph Company, At&T Bell Laboratories Interleaved set-associative memory
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
US4835678A (en) * 1985-02-01 1989-05-30 Nec Corporation Cache memory circuit for processing a read request during transfer of a data block
US4630239A (en) * 1985-07-01 1986-12-16 Motorola, Inc. Chip select speed-up circuit for a memory
JPS6261135A (ja) * 1985-09-11 1987-03-17 Nec Corp キヤツシユメモリ
JPS62194563A (ja) * 1986-02-21 1987-08-27 Hitachi Ltd バツフア記憶装置
US4710903A (en) * 1986-03-31 1987-12-01 Wang Laboratories, Inc. Pseudo-static memory subsystem
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access

Also Published As

Publication number Publication date
DE68924368T2 (de) 1996-05-02
DK189689D0 (da) 1989-04-19
GB2219111B (en) 1991-05-29
DE68924368D1 (de) 1995-11-02
GB2219111A (en) 1989-11-29
CN1040104A (zh) 1990-02-28
FR2632092A1 (fr) 1989-12-01
KR930001584B1 (ko) 1993-03-05
CN1019151B (zh) 1992-11-18
DK170677B1 (da) 1995-11-27
BE1002653A4 (fr) 1991-04-23
EP0343989A3 (en) 1991-03-13
NO891583D0 (no) 1989-04-18
DE3911721A1 (de) 1989-11-30
US5175826A (en) 1992-12-29
AU615542B2 (en) 1991-10-03
SG110991G (en) 1992-02-14
SE8901308D0 (sv) 1989-04-11
HK11592A (en) 1992-02-21
JP2755330B2 (ja) 1998-05-20
IT1230208B (it) 1991-10-18
MY106968A (en) 1995-08-30
KR890017619A (ko) 1989-12-16
BR8902383A (pt) 1990-01-16
GB8912019D0 (en) 1989-07-12
AU3409689A (en) 1989-11-30
DK189689A (da) 1989-11-27
GB8904920D0 (en) 1989-04-12
SE8901308L (sv) 1989-11-27
FI891788A7 (fi) 1989-11-27
NO891583L (no) 1989-11-27
FI96244B (fi) 1996-02-15
NL8901327A (nl) 1989-12-18
ATE128566T1 (de) 1995-10-15
ES2078237T3 (es) 1995-12-16
EP0343989B1 (en) 1995-09-27
CO4520299A1 (es) 1997-10-15
NO175837C (no) 1994-12-14
DE3911721C2 (es) 1990-05-31
FI891788A0 (fi) 1989-04-14
CA1314103C (en) 1993-03-02
IT8920649A0 (it) 1989-05-25
FI96244C (fi) 1996-05-27
JPH0271344A (ja) 1990-03-09
EP0343989A2 (en) 1989-11-29
NO175837B (no) 1994-09-05

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