JPS6412349A - System for controlling buffer invalidation processor - Google Patents

System for controlling buffer invalidation processor

Info

Publication number
JPS6412349A
JPS6412349A JP62168263A JP16826387A JPS6412349A JP S6412349 A JPS6412349 A JP S6412349A JP 62168263 A JP62168263 A JP 62168263A JP 16826387 A JP16826387 A JP 16826387A JP S6412349 A JPS6412349 A JP S6412349A
Authority
JP
Japan
Prior art keywords
turned
processor
register
request
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62168263A
Other languages
Japanese (ja)
Other versions
JPH0721780B2 (en
Inventor
Motoyoshi Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62168263A priority Critical patent/JPH0721780B2/en
Publication of JPS6412349A publication Critical patent/JPS6412349A/en
Publication of JPH0721780B2 publication Critical patent/JPH0721780B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent performance from being lowered, by outputting a buffer invalidating request to all processors other tan the processor, to whose memory device information is written, when the number of separating ways due to an error exceeds a prescribed threshold value. CONSTITUTION:The address STADR of a write request STREQ from the processor is set at an address register 7, and a TAG28 is retrieved. Out of coincidence signals taken by comparators 91-9n, the signal that coincides with the output of a register 11 which holes the separating WAY is suppressed by an AND circuit 10. And an invalidation request BiREQ is turned ON in a case where an AND circuit 14 turned ON when all of the outputs of the register 11 are turned ON is turned ON, or when even one coincidence signal is obtained.
JP62168263A 1987-07-06 1987-07-06 Buffer invalidation processor Expired - Lifetime JPH0721780B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168263A JPH0721780B2 (en) 1987-07-06 1987-07-06 Buffer invalidation processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168263A JPH0721780B2 (en) 1987-07-06 1987-07-06 Buffer invalidation processor

Publications (2)

Publication Number Publication Date
JPS6412349A true JPS6412349A (en) 1989-01-17
JPH0721780B2 JPH0721780B2 (en) 1995-03-08

Family

ID=15864769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168263A Expired - Lifetime JPH0721780B2 (en) 1987-07-06 1987-07-06 Buffer invalidation processor

Country Status (1)

Country Link
JP (1) JPH0721780B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6327225B1 (en) 1998-12-14 2001-12-04 Seiko Epson Corporation Electronic unit, and control method for electronic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6327225B1 (en) 1998-12-14 2001-12-04 Seiko Epson Corporation Electronic unit, and control method for electronic unit

Also Published As

Publication number Publication date
JPH0721780B2 (en) 1995-03-08

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