KR970700375A - 적층 저유전상수 기술(layered low dielectric constant technology) - Google Patents

적층 저유전상수 기술(layered low dielectric constant technology)

Info

Publication number
KR970700375A
KR970700375A KR1019960703518A KR19960703518A KR970700375A KR 970700375 A KR970700375 A KR 970700375A KR 1019960703518 A KR1019960703518 A KR 1019960703518A KR 19960703518 A KR19960703518 A KR 19960703518A KR 970700375 A KR970700375 A KR 970700375A
Authority
KR
South Korea
Prior art keywords
layer
sog
metal
inorganic
metal wiring
Prior art date
Application number
KR1019960703518A
Other languages
English (en)
Other versions
KR100392900B1 (ko
Inventor
로빈 더블유. 청
Original Assignee
미키오 이시마루
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미키오 이시마루, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 미키오 이시마루
Publication of KR970700375A publication Critical patent/KR970700375A/ko
Application granted granted Critical
Publication of KR100392900B1 publication Critical patent/KR100392900B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Organic Insulating Materials (AREA)
  • Inorganic Insulating Materials (AREA)

Abstract

본 발명의 적층 유전체 구조는 상기 제1금속배선층(12)에서 금속배선들 사이에 갭을 채워주는 유기성 에스오지(SOG) 층(18)과; 상기 제2금속배선층(28)를 지지하기 위해 표면을 평평하게 만들어 주는 무기성 에스오지(SOG) 층(26); 상기 무기성 에스오지(SOG) 층(26)과 상기 유기성 에스오지(SOG) 층(18)을 분리시켜 주는 화학증착 산화층(20)으로 구성이 된 것을 특징으로 하여, 반도체 소자내에서 제1금속배선층을 서로 분리시켜 주고, 제2금속배선층(28)과 상기 제1금속배선층(12)을 분리시키며, 상기 제1금속배선층(12)과 전기적으로 접속시키기 위한 제2금속층(28)이 그의(12) 상부를 덮어씌우고 있다. 이와 같이 본 발명에 따른 다층 구조로 이루어진 유전체 구조는, 수직방향으로는 3.36에서 3.46, 수평방향으로는 3.2에 이르는 정전 용량을 가지고 있다. 이것은 종래의 1개층을 구비한 유전층에 비해 10 내지 15%이상 감소한 것이다.

Description

적층 저유전상수 기술(LAYERED LOW DIELECTRIC CONSTANT TECHNOLOGY)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (10)

  1. 제1금속배선층(12)에서 금속배선들 사이의 갭을 채워주는 유기성 에스오지(SOG) 층(18)과; 제2금속배선층(28)을 지지하기 위해 표면을 평평하게 만들어 주는 무기성 에스오지(SOG)층(16); 상기 무기성 에스오지(SOG)층(26)과 상기 유기성 에스오지(SOG) 층(18)을 분리시켜 주는 화학증착 산화층(20)으로 구성되어, 반도체 소자내에서 제1금속배선층을 서로 분리시켜 주고, 제2금속배선층(28)과 상기 제1금속배선층(12)을 분리시키며, 상기 제1금속배선층(12)과 전기적으로 접속시키기 위한 제2금속층(28)이 그의(12) 상부를 덮어씌우고 있는 적층 유전체 구조.
  2. 제1항에 있어서, 상기 유기성 에스오지(SOG) 층은 고탄소 함유 실록산으로 이루어진 것을 특징으로 하는 적층 유전체 구조.
  3. 제2항에 있어서, 상기 유기성 에스오지(SOG) 층(18)은 상기 제1금속배선층(12)의 두께의 1/2정도의 두께를 가지는 것을 특징으로 하는 적층 유전체 구조.
  4. 제1항에 있어서, 상기 무기성 에스오지(SOG) 층(26)은 규산염이나 수소 실세스퀴녹센으로 이루어진 것을 특징으로 하는 적층 유전체 구조.
  5. 제4항에 있어서, 상기 무기성 에스오지(SOG) 층(26)의 두께는 약 6,000Å 미만으로 된 것을 특징으로 하는 적층 유전체 구조.
  6. 제1항에 있어서, 상기 화학증착 산화층(20)은 실리콘을 다량 함유한 실리콘 이산화물로 구성된 것을 특징으로 하는 적층 유전체 구조.
  7. 제6항에 있어서, 상기 화학증착 산화층(20)은 약 500 내지 1,000Å의 두께를 가지는 것을 특징으로 하는 적층 유전체 구조.
  8. 제1항에 있어서, 상기 적층형 유전 구조는, 상기 제1금속배선층(12)의 노출된 금속 표면과 반도체 기판의 노출된 표면을 코팅하여 산화물로 코팅된 금속배선들(12)을 형성하는 플라즈마가 강화된 제1화학증착 산화물층(16); 상기 금속배선들 사이의 공간은 부분적으로 채우고 상기 산화물이 코팅된 금속배선들(12)의 상면은 노출되게 두는 유기성 에스오지(SOG) 층(18); 상기 산화 코팅된 금속배선(12)의 상면과 상기 유기성 에스오지(SOG)층(18)의 상면에 위치한 플라즈마가 강화된 제2화학증착층(20); 상기 플라즈마가 강화된 제2화학증착 산화층(20)을 코팅하는 제1무기성 에스오지(SOG) 층(22); 상기 제1무기성 에스오지(SOG) 층(22)을 코팅하는 플라즈마가 강화된 제3화학증착 산화층(24); 상기 플라즈마가 강화된 제3화학증착 산화층(24)을 코팅하는 제2무기성 평면 에스오지(SOG) 층(26); 그리고 상기 제2무기성 에스오지(SOG) 층(26)의 상면에 위치한 상기 제2층의 금속 인터컨넥터층(28)으로 구성된 것을 특징으로 하는 적층 유전체 구조.
  9. 제1금속배선층에서 그 금속배선들(12) 사이에 갭을 채워주는 유기성 에스오지(SOG) 재질의 층(18)을 형성하는 공정; 상기 유기성 에스오지(SOG) 층(18)위에 화학적으로 기상 증착된 산화층(20)을 형성하는 공정; 그리고 제2금속배선층(28)을 지지하고 표면을 평평하게 만들어 주기위하여 상기 화학 기상 증착 산화층(20) 위에 위치한 상기 무기성 에스오지(SOG) 층(26)을 형성하는 공정으로 구성되어, 상기 제1금속배선층(12)들 서로를 분리시키고 동시에 상기 제2금속배선층으로부터도 분리시키며, 상기 유전물질에 의해 상기 제1금속배선층을 전기적으로 접속시키기 위한 금속배선층(28)이 덮여 있어서, 제1항의 상기 반도체 소자내에서 상기 제1금속배선층들 사이의 정전용량을 줄이기 위한 방법.
  10. 제9항에 있어서, 상기 제1금속배선(12)층의 노출된 금속 표면과 노출된 반도체 기판 표면에, 산화 코팅된 금속배선(12)을 형성하기 위하여, 상기 플라즈마가 강화된 화학증착 산화층(16)을 형성하는 공정; 상기 제1금속배선(12)들 사이를 부분적으로 채워주고 상기 산화 코팅된 금속배선들의 상면을 노출시켜 두는 유기성 에스오지(SOG) 층(18)을 형성하는 공정; 상기 산화 코팅된 금속배선들(12)의 상면과 상기 유기성 에스오지(SOG) 층(18)의 상면에 플라즈마가 강화된 제2화학증착 산화층(20)을 형성하는 공정; 상기 플라즈마가 강화된 제2화학증착 산화층(20) 위에 제1무기성 에스오지(SOG) 층(22)을 형성하는 공정; 상기 제1무기성 에스오지(SOG) 층(22)위에 플라즈마가 강화된 제3화학증착 산화층(24)을 형성하는 공정; 상기 플라즈마가 강화된 제3화학증착 산화층(24)위에 표면이 평평하게 형성된 제2무기성 에스오지(SOG) 층(26)을 형성하는 공정; 그리고 상기 제2무기성 에스오지(SOG) 층(26)의 상면에 제2금속배선층(28)을 형성하는 공정으로 구성된 것을 특징으로 하는 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960703518A 1994-10-28 1995-09-29 적층저유전상수기술 KR100392900B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/330,871 US5534731A (en) 1994-10-28 1994-10-28 Layered low dielectric constant technology
US08/330871 1994-10-28

Publications (2)

Publication Number Publication Date
KR970700375A true KR970700375A (ko) 1997-01-08
KR100392900B1 KR100392900B1 (ko) 2003-11-17

Family

ID=23291661

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960703518A KR100392900B1 (ko) 1994-10-28 1995-09-29 적층저유전상수기술

Country Status (8)

Country Link
US (2) US5534731A (ko)
EP (1) EP0737362B1 (ko)
JP (1) JPH09507617A (ko)
KR (1) KR100392900B1 (ko)
AT (1) ATE187015T1 (ko)
DE (1) DE69513501T2 (ko)
TW (1) TW260824B (ko)
WO (1) WO1996013856A1 (ko)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3214186B2 (ja) * 1993-10-07 2001-10-02 三菱電機株式会社 半導体装置の製造方法
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5395785A (en) 1993-12-17 1995-03-07 Sgs-Thomson Microelectronics, Inc. SRAM cell fabrication with interlevel dielectric planarization
GB9412178D0 (en) * 1994-06-17 1994-08-10 Dow Corning Sa Foam control agent
US5889330A (en) * 1995-03-10 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device whose flattening resin film component has a controlled carbon atom content
US5599745A (en) * 1995-06-07 1997-02-04 Micron Technology, Inc. Method to provide a void between adjacent conducting lines in a semiconductor device
US5955786A (en) * 1995-06-07 1999-09-21 Advanced Micro Devices, Inc. Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines
US5814186A (en) * 1995-08-28 1998-09-29 Advanced Micro Devices, Inc. SOG etchant gas and method for using same
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US5849640A (en) * 1996-04-01 1998-12-15 Vanguard International Semiconductor Corporation In-situ SOG etchback and deposition for IMD process
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US5923074A (en) * 1996-12-03 1999-07-13 Texas Instruments Incorporated Low capacitance interconnect structure for integrated circuits using decomposed polymers
TW571373B (en) * 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
US5691247A (en) * 1996-12-19 1997-11-25 Tower Semiconductor Ltd. Method for depositing a flow fill layer on an integrated circuit wafer
DE69820232T2 (de) * 1997-01-21 2004-09-16 Georgia Tech Research Corp. Verfahren zur herstellung einer halbleitervorrichtung mit luftspalten für verbindungen mit ultraniedriger kapazität
US5963837A (en) * 1997-04-30 1999-10-05 Siemens Aktiengesellschaft Method of planarizing the semiconductor structure
JPH10321631A (ja) * 1997-05-19 1998-12-04 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
US6048803A (en) * 1997-08-19 2000-04-11 Advanced Microdevices, Inc. Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines
US5962067A (en) 1997-09-09 1999-10-05 Lucent Technologies Inc. Method for coating an article with a ladder siloxane polymer and coated article
US5866945A (en) * 1997-10-16 1999-02-02 Advanced Micro Devices Borderless vias with HSQ gap filled patterned metal layers
US6083850A (en) * 1997-12-18 2000-07-04 Advanced Micro Devices, Inc. HSQ dielectric interlayer
US6162743A (en) * 1998-02-10 2000-12-19 Chu; Cheng-Jye Low dielectric constant film and method thereof
US6376359B1 (en) * 1998-03-18 2002-04-23 United Microelectronics Corp. Method of manufacturing metallic interconnect
US6396145B1 (en) * 1998-06-12 2002-05-28 Hitachi, Ltd. Semiconductor device and method for manufacturing the same technical field
US6080676A (en) * 1998-09-17 2000-06-27 Advanced Micro Devices, Inc. Device and method for etching spacers formed upon an integrated circuit gate conductor
US6281132B1 (en) 1998-10-06 2001-08-28 Advanced Micro Devices, Inc. Device and method for etching nitride spacers formed upon an integrated circuit gate conductor
US6444564B1 (en) 1998-11-23 2002-09-03 Advanced Micro Devices, Inc. Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
US6770975B2 (en) * 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
JP2001044191A (ja) * 1999-07-27 2001-02-16 Sony Corp 積層絶縁膜とその製造方法および半導体装置とその製造方法
GB2358733A (en) * 1999-08-30 2001-08-01 Lucent Technologies Inc Integrated circuit with multi-layer dielectric having reduced capacitance
GB2358734A (en) * 1999-08-30 2001-08-01 Lucent Technologies Inc Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US7211512B1 (en) 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US7262130B1 (en) 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
JP2001284450A (ja) 2000-04-03 2001-10-12 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6891237B1 (en) 2000-06-27 2005-05-10 Lucent Technologies Inc. Organic semiconductor device having an active dielectric layer comprising silsesquioxanes
US6794705B2 (en) * 2000-12-28 2004-09-21 Infineon Technologies Ag Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
DE10146146B4 (de) * 2001-09-19 2004-02-05 Infineon Technologies Ag Verfahren zur elektrischen Isolation nebeneinander liegender metallischer Leiterbahnen und Halbleiterbauelement mit voneinander isolierten metallischen Leiterbahnen
US7208426B2 (en) * 2001-11-13 2007-04-24 Chartered Semiconductors Manufacturing Limited Preventing plasma induced damage resulting from high density plasma deposition
US7001389B1 (en) 2002-07-05 2006-02-21 Navarro Richard R Fixed and variable locking fixation assembly
US6927180B2 (en) * 2002-11-27 2005-08-09 Intel Corporation Reducing line to line capacitance using oriented dielectric films
US7060554B2 (en) * 2003-07-11 2006-06-13 Advanced Micro Devices, Inc. PECVD silicon-rich oxide layer for reduced UV charging
US7033897B2 (en) * 2003-10-23 2006-04-25 Texas Instruments Incorporated Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
US7524735B1 (en) 2004-03-25 2009-04-28 Novellus Systems, Inc Flowable film dielectric gap fill process
US7582555B1 (en) * 2005-12-29 2009-09-01 Novellus Systems, Inc. CVD flowable gap fill
US9257302B1 (en) 2004-03-25 2016-02-09 Novellus Systems, Inc. CVD flowable gap fill
US7670961B2 (en) * 2004-06-08 2010-03-02 Nxp B.V. Reduction of cracking in low-k spin-on dielectric films
TW200605220A (en) * 2004-06-21 2006-02-01 Hitachi Chemical Co Ltd Organic siloxane film, semiconductor device using same, flat panel display and raw material liquid
US7285474B2 (en) * 2004-09-16 2007-10-23 International Business Machines Corporation Air-gap insulated interconnections
KR100713985B1 (ko) * 2005-05-16 2007-05-04 삼성에스디아이 주식회사 박막트랜지스터 및 박막트랜지스터 제조방법
JP2007273494A (ja) * 2006-03-30 2007-10-18 Fujitsu Ltd 絶縁膜形成用組成物及び半導体装置の製造方法
US9245739B2 (en) 2006-11-01 2016-01-26 Lam Research Corporation Low-K oxide deposition by hydrolysis and condensation
US7927990B2 (en) * 2007-06-29 2011-04-19 Sandisk Corporation Forming complimentary metal features using conformal insulator layer
US8557712B1 (en) 2008-12-15 2013-10-15 Novellus Systems, Inc. PECVD flowable dielectric gap fill
US8278224B1 (en) 2009-09-24 2012-10-02 Novellus Systems, Inc. Flowable oxide deposition using rapid delivery of process gases
US8728958B2 (en) * 2009-12-09 2014-05-20 Novellus Systems, Inc. Gap fill integration
US8685867B1 (en) 2010-12-09 2014-04-01 Novellus Systems, Inc. Premetal dielectric integration process
US9719169B2 (en) 2010-12-20 2017-08-01 Novellus Systems, Inc. System and apparatus for flowable deposition in semiconductor fabrication
US8846536B2 (en) 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
US9847222B2 (en) 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US10049921B2 (en) 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric
US9916977B2 (en) 2015-11-16 2018-03-13 Lam Research Corporation Low k dielectric deposition via UV driven photopolymerization
US12060639B2 (en) 2019-04-19 2024-08-13 Lam Research Corporation Rapid flush purging during atomic layer deposition

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4185294A (en) * 1975-12-10 1980-01-22 Tokyo Shibaura Electric Co., Ltd. Semiconductor device and a method for manufacturing the same
US4939559A (en) * 1981-12-14 1990-07-03 International Business Machines Corporation Dual electron injector structures using a conductive oxide between injectors
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
WO1989005519A1 (en) * 1987-12-02 1989-06-15 Advanced Micro Devices, Inc. Self-aligned interconnects for semiconductor devices
US5055427A (en) * 1987-12-02 1991-10-08 Advanced Micro Devices, Inc. Process of forming self-aligned interconnects for semiconductor devices
US5028555A (en) * 1987-12-02 1991-07-02 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
US4977108A (en) * 1987-12-02 1990-12-11 Advanced Micro Devices, Inc. Method of making self-aligned, planarized contacts for semiconductor devices
US5081516A (en) * 1987-12-02 1992-01-14 Advanced Micro Devices, Inc. Self-aligned, planarized contacts for semiconductor devices
US5057902A (en) * 1987-12-02 1991-10-15 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
JPH03196663A (ja) * 1989-12-26 1991-08-28 Fujitsu Ltd 半導体装置の製造方法
US5250468A (en) * 1990-02-05 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including interlaying insulating film
US5374833A (en) * 1990-03-05 1994-12-20 Vlsi Technology, Inc. Structure for suppression of field inversion caused by charge build-up in the dielectric
US5057897A (en) * 1990-03-05 1991-10-15 Vlsi Technology, Inc. Charge neutralization using silicon-enriched oxide layer
US5043789A (en) * 1990-03-15 1991-08-27 International Business Machines Corporation Planarizing silsesquioxane copolymer coating
JPH0529481A (ja) * 1991-07-25 1993-02-05 Nec Corp 半導体装置
CA2056456C (en) * 1991-08-14 2001-05-08 Luc Ouellet High performance passivation for semiconductor devices
US5393702A (en) * 1993-07-06 1995-02-28 United Microelectronics Corporation Via sidewall SOG nitridation for via filling
US5441765A (en) * 1993-09-22 1995-08-15 Dow Corning Corporation Method of forming Si-O containing coatings
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5407860A (en) * 1994-05-27 1995-04-18 Texas Instruments Incorporated Method of forming air gap dielectric spaces between semiconductor leads

Also Published As

Publication number Publication date
KR100392900B1 (ko) 2003-11-17
US5534731A (en) 1996-07-09
WO1996013856A1 (en) 1996-05-09
US5693566A (en) 1997-12-02
ATE187015T1 (de) 1999-12-15
DE69513501T2 (de) 2000-06-29
EP0737362A1 (en) 1996-10-16
EP0737362B1 (en) 1999-11-24
DE69513501D1 (de) 1999-12-30
JPH09507617A (ja) 1997-07-29
TW260824B (en) 1995-10-21

Similar Documents

Publication Publication Date Title
KR970700375A (ko) 적층 저유전상수 기술(layered low dielectric constant technology)
US5441915A (en) Process of fabrication planarized metallurgy structure for a semiconductor device
US6303457B1 (en) Integrated circuit having integral decoupling capacitor
US7371461B2 (en) Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
TW477028B (en) Hybrid dielectric structure for improving the stiffness of back end of the line structures
JPH01235254A (ja) 半導体装置及びその製造方法
JPS6432663A (en) Multilayer interconnection system for multi-chip high performance semiconductor package
KR970072315A (ko) 반도체소자의 다층배선 형성방법
KR910013465A (ko) 도전 재료의 선택적 형성방법
KR970053361A (ko) 반도체 소자 및 그 제조 방법
CA2056456A1 (en) High performance passivation for semiconductor devices
JPS5968953A (ja) モノリシツク集積回路の製造方法
US6797615B1 (en) Method of manufacturing a semiconductor device
US4601939A (en) Composite insulator structure
CN1327508C (zh) 半导体装置的制造方法
KR930003279A (ko) 반도체장치의 표면 평탄화 방법
KR20040098952A (ko) 반도체 금속 배선 공정에서의 산화막 형성 방법
KR940006199A (ko) 상호 접속 배선 구조물을 갖는 반도체 디바이스
KR20010061495A (ko) 반도체 소자의 층간 절연막용 붕소화 실리콘 탄화막 및이를 이용한 금속 배선 형성 방법
KR100254471B1 (ko) 금속배선층간 절연막 평탄화방법
KR950030263A (ko) 반도체장치 제조방법
KR900013583A (ko) 반도체 소자의 접속장치
KR19990074940A (ko) 측벽에 불소 차단막을 갖는 금속 배선 형성 방법
JPS5843538A (ja) 半導体集積回路装置
JPH09326434A (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20131226

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20140627

Year of fee payment: 12

EXPY Expiration of term