KR970700375A - 적층 저유전상수 기술(layered low dielectric constant technology) - Google Patents
적층 저유전상수 기술(layered low dielectric constant technology)Info
- Publication number
- KR970700375A KR970700375A KR1019960703518A KR19960703518A KR970700375A KR 970700375 A KR970700375 A KR 970700375A KR 1019960703518 A KR1019960703518 A KR 1019960703518A KR 19960703518 A KR19960703518 A KR 19960703518A KR 970700375 A KR970700375 A KR 970700375A
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- metal
- inorganic
- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Organic Insulating Materials (AREA)
- Inorganic Insulating Materials (AREA)
Abstract
본 발명의 적층 유전체 구조는 상기 제1금속배선층(12)에서 금속배선들 사이에 갭을 채워주는 유기성 에스오지(SOG) 층(18)과; 상기 제2금속배선층(28)를 지지하기 위해 표면을 평평하게 만들어 주는 무기성 에스오지(SOG) 층(26); 상기 무기성 에스오지(SOG) 층(26)과 상기 유기성 에스오지(SOG) 층(18)을 분리시켜 주는 화학증착 산화층(20)으로 구성이 된 것을 특징으로 하여, 반도체 소자내에서 제1금속배선층을 서로 분리시켜 주고, 제2금속배선층(28)과 상기 제1금속배선층(12)을 분리시키며, 상기 제1금속배선층(12)과 전기적으로 접속시키기 위한 제2금속층(28)이 그의(12) 상부를 덮어씌우고 있다. 이와 같이 본 발명에 따른 다층 구조로 이루어진 유전체 구조는, 수직방향으로는 3.36에서 3.46, 수평방향으로는 3.2에 이르는 정전 용량을 가지고 있다. 이것은 종래의 1개층을 구비한 유전층에 비해 10 내지 15%이상 감소한 것이다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
Claims (10)
- 제1금속배선층(12)에서 금속배선들 사이의 갭을 채워주는 유기성 에스오지(SOG) 층(18)과; 제2금속배선층(28)을 지지하기 위해 표면을 평평하게 만들어 주는 무기성 에스오지(SOG)층(16); 상기 무기성 에스오지(SOG)층(26)과 상기 유기성 에스오지(SOG) 층(18)을 분리시켜 주는 화학증착 산화층(20)으로 구성되어, 반도체 소자내에서 제1금속배선층을 서로 분리시켜 주고, 제2금속배선층(28)과 상기 제1금속배선층(12)을 분리시키며, 상기 제1금속배선층(12)과 전기적으로 접속시키기 위한 제2금속층(28)이 그의(12) 상부를 덮어씌우고 있는 적층 유전체 구조.
- 제1항에 있어서, 상기 유기성 에스오지(SOG) 층은 고탄소 함유 실록산으로 이루어진 것을 특징으로 하는 적층 유전체 구조.
- 제2항에 있어서, 상기 유기성 에스오지(SOG) 층(18)은 상기 제1금속배선층(12)의 두께의 1/2정도의 두께를 가지는 것을 특징으로 하는 적층 유전체 구조.
- 제1항에 있어서, 상기 무기성 에스오지(SOG) 층(26)은 규산염이나 수소 실세스퀴녹센으로 이루어진 것을 특징으로 하는 적층 유전체 구조.
- 제4항에 있어서, 상기 무기성 에스오지(SOG) 층(26)의 두께는 약 6,000Å 미만으로 된 것을 특징으로 하는 적층 유전체 구조.
- 제1항에 있어서, 상기 화학증착 산화층(20)은 실리콘을 다량 함유한 실리콘 이산화물로 구성된 것을 특징으로 하는 적층 유전체 구조.
- 제6항에 있어서, 상기 화학증착 산화층(20)은 약 500 내지 1,000Å의 두께를 가지는 것을 특징으로 하는 적층 유전체 구조.
- 제1항에 있어서, 상기 적층형 유전 구조는, 상기 제1금속배선층(12)의 노출된 금속 표면과 반도체 기판의 노출된 표면을 코팅하여 산화물로 코팅된 금속배선들(12)을 형성하는 플라즈마가 강화된 제1화학증착 산화물층(16); 상기 금속배선들 사이의 공간은 부분적으로 채우고 상기 산화물이 코팅된 금속배선들(12)의 상면은 노출되게 두는 유기성 에스오지(SOG) 층(18); 상기 산화 코팅된 금속배선(12)의 상면과 상기 유기성 에스오지(SOG)층(18)의 상면에 위치한 플라즈마가 강화된 제2화학증착층(20); 상기 플라즈마가 강화된 제2화학증착 산화층(20)을 코팅하는 제1무기성 에스오지(SOG) 층(22); 상기 제1무기성 에스오지(SOG) 층(22)을 코팅하는 플라즈마가 강화된 제3화학증착 산화층(24); 상기 플라즈마가 강화된 제3화학증착 산화층(24)을 코팅하는 제2무기성 평면 에스오지(SOG) 층(26); 그리고 상기 제2무기성 에스오지(SOG) 층(26)의 상면에 위치한 상기 제2층의 금속 인터컨넥터층(28)으로 구성된 것을 특징으로 하는 적층 유전체 구조.
- 제1금속배선층에서 그 금속배선들(12) 사이에 갭을 채워주는 유기성 에스오지(SOG) 재질의 층(18)을 형성하는 공정; 상기 유기성 에스오지(SOG) 층(18)위에 화학적으로 기상 증착된 산화층(20)을 형성하는 공정; 그리고 제2금속배선층(28)을 지지하고 표면을 평평하게 만들어 주기위하여 상기 화학 기상 증착 산화층(20) 위에 위치한 상기 무기성 에스오지(SOG) 층(26)을 형성하는 공정으로 구성되어, 상기 제1금속배선층(12)들 서로를 분리시키고 동시에 상기 제2금속배선층으로부터도 분리시키며, 상기 유전물질에 의해 상기 제1금속배선층을 전기적으로 접속시키기 위한 금속배선층(28)이 덮여 있어서, 제1항의 상기 반도체 소자내에서 상기 제1금속배선층들 사이의 정전용량을 줄이기 위한 방법.
- 제9항에 있어서, 상기 제1금속배선(12)층의 노출된 금속 표면과 노출된 반도체 기판 표면에, 산화 코팅된 금속배선(12)을 형성하기 위하여, 상기 플라즈마가 강화된 화학증착 산화층(16)을 형성하는 공정; 상기 제1금속배선(12)들 사이를 부분적으로 채워주고 상기 산화 코팅된 금속배선들의 상면을 노출시켜 두는 유기성 에스오지(SOG) 층(18)을 형성하는 공정; 상기 산화 코팅된 금속배선들(12)의 상면과 상기 유기성 에스오지(SOG) 층(18)의 상면에 플라즈마가 강화된 제2화학증착 산화층(20)을 형성하는 공정; 상기 플라즈마가 강화된 제2화학증착 산화층(20) 위에 제1무기성 에스오지(SOG) 층(22)을 형성하는 공정; 상기 제1무기성 에스오지(SOG) 층(22)위에 플라즈마가 강화된 제3화학증착 산화층(24)을 형성하는 공정; 상기 플라즈마가 강화된 제3화학증착 산화층(24)위에 표면이 평평하게 형성된 제2무기성 에스오지(SOG) 층(26)을 형성하는 공정; 그리고 상기 제2무기성 에스오지(SOG) 층(26)의 상면에 제2금속배선층(28)을 형성하는 공정으로 구성된 것을 특징으로 하는 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/330,871 US5534731A (en) | 1994-10-28 | 1994-10-28 | Layered low dielectric constant technology |
US08/330871 | 1994-10-28 |
Publications (2)
Publication Number | Publication Date |
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KR970700375A true KR970700375A (ko) | 1997-01-08 |
KR100392900B1 KR100392900B1 (ko) | 2003-11-17 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019960703518A KR100392900B1 (ko) | 1994-10-28 | 1995-09-29 | 적층저유전상수기술 |
Country Status (8)
Country | Link |
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US (2) | US5534731A (ko) |
EP (1) | EP0737362B1 (ko) |
JP (1) | JPH09507617A (ko) |
KR (1) | KR100392900B1 (ko) |
AT (1) | ATE187015T1 (ko) |
DE (1) | DE69513501T2 (ko) |
TW (1) | TW260824B (ko) |
WO (1) | WO1996013856A1 (ko) |
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-
1994
- 1994-10-28 US US08/330,871 patent/US5534731A/en not_active Expired - Lifetime
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1995
- 1995-04-01 TW TW084103211A patent/TW260824B/zh active
- 1995-06-02 US US08/459,957 patent/US5693566A/en not_active Expired - Lifetime
- 1995-09-29 JP JP8514582A patent/JPH09507617A/ja not_active Ceased
- 1995-09-29 KR KR1019960703518A patent/KR100392900B1/ko not_active IP Right Cessation
- 1995-09-29 WO PCT/US1995/012594 patent/WO1996013856A1/en active IP Right Grant
- 1995-09-29 EP EP95935248A patent/EP0737362B1/en not_active Expired - Lifetime
- 1995-09-29 AT AT95935248T patent/ATE187015T1/de not_active IP Right Cessation
- 1995-09-29 DE DE69513501T patent/DE69513501T2/de not_active Expired - Fee Related
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KR100392900B1 (ko) | 2003-11-17 |
US5534731A (en) | 1996-07-09 |
WO1996013856A1 (en) | 1996-05-09 |
US5693566A (en) | 1997-12-02 |
ATE187015T1 (de) | 1999-12-15 |
DE69513501T2 (de) | 2000-06-29 |
EP0737362A1 (en) | 1996-10-16 |
EP0737362B1 (en) | 1999-11-24 |
DE69513501D1 (de) | 1999-12-30 |
JPH09507617A (ja) | 1997-07-29 |
TW260824B (en) | 1995-10-21 |
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