GB2358733A

GB2358733A - Integrated circuit with multi-layer dielectric having reduced capacitance

Info

Publication number: GB2358733A
Application number: GB0019968A
Authority: GB
Inventors: Jr Gerald W Gibson; Steven Alan Lytle; Mary Drummond Roby; Daniel Joseph Vitkavage; Thomas Michael Wolf
Original assignee: Lucent Technologies Inc
Current assignee: Nokia of America Corp
Priority date: 1999-08-30
Filing date: 2000-08-14
Publication date: 2001-08-01
Also published as: GB0019968D0; JP2001102377A; KR20010030169A

Abstract

An integrated circuit comprises dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100). The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO<SB>2</SB>) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

Description

2358733 Reduced Capacitance Dielectric Structure For Integrated Circuits

Cross Reference to Related Applications

The present invention is related to U. S. Patent Application No. 09/385714, filed 8/30/99 (Attorney Docket No. Gibson 4-13-3-17-11) the disclosure of which is specifically incorporated herein by reference.

Field of the Invention

The present invention relates to an integrated circuit structure having reduced line-to-line capacitance.

Background of the Inventio

Integration and miniaturization in integrated circuits has resulted in a reduction in spacing between features in the integrated circuit. This reduction has resulted in the intralevel conductor or line-to-line capacitance (CL-L) being the dominant component of parasitic capacitance within the integrated circuit. Materials having a low dielectric constant are used often as the inter-layer dielectric (ELD) within the integrated circuit to help reduce line-to-line capacitance.

The problem of increased CL-L may affect dual damascene conductor structures which combine trenches and vias. Accordingly, low dielectric constant (low-k) materials are used in conjunction with dual damascene structures. One technique is to use a single layer of low-k dielectric for both the trench and via layers. While the use of a single low-k dielectric layer may aid in reducing the line-to-line capacitance, fabricating a dual damascene structure with a single low-k layer may be difficult. The process requires the trench etch to be extremely well controlled. The trench etch must have excellent within wafer and wafer-to- wafer uniformity and the etch rate must be independent of the trench width. Furthermore, the bottom of the trench must be made substantially flat. This is difficult to obtain using many conventional etch tools.

1 - Another technique to incorporate low-k material in a dual damascene structure uses an etch-stop layer between the trench layer and the via layer (again the same material is used for both the trench and via layers). While the etch-stop layer enables a highly selective etch between the trench and via dielectric layers the etch stop process is relatively complicated. The etch stop layer adds another step to the deposition process and in many cases the deposition tools needed for the etch stop are not the same as those used for the deposition of the trench and via dielectrics. This increases processing time and cost. Finally, control of the three layer film stack is difficult since optical film thickness measurements commonly used are difficult to perform on such complex structures.

In addition to the drawbacks discussed above, many of the available low-k dielectric materials are soft compared to silicon dioxide and have a poor thermal conductivity creating bonding and heat dissipation problems. Thus the use of a single layer of low-k material for reducing CL-L may not be practical.

Accordingly, what is needed is an altemative structure for reducing the line-to-line capacitance in integrated circuits.

Summa.ty of the Invention The present invention relates to an integrated circuit having a multilayer dielectric that reduces line-to-line capacitance (CL-L). The multi-layer dielectric includes a first dielectric layer having a second dielectric layer disposed thereover. The second dielectric layer includes a low dielectric constant (low-k) material that reduces the overall dielectric constant of the inter-layer dielectric (ILD). The first dielectric layer provides structural support to the second dielectric layer and has thermal characteristics which aid in dissipating heat from the integrated circuit. By virtue of the reduced dielectric constant of the H.D, intra-level or line-to-line capacitance in the integrated circuit may be reduced.

Brief DesgEiption of the Drawin The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that in accordance with common practice in the semiconductor industry, the various features are not necessarily to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity.

Figure I is a cross sectional view of an exemplary embodiment of the invention of the present disclosure.

Figures 2(a)-2(e) are cross-sectional views of an exemplary embodiment of the present invention showing a process sequence for its fabrication.

Figure 3 is an exemplary embodiment of the present invention.

Figure 4 is an exemplary embodiment of the present invention.

Detailed Desgdption of the Invention Briefly, the present invention is directed to an integrated circuit and its method of manufacture having a multi-layer dielectric which has a second dielectric layer for reducing Ene-to-line capacitance and a first layer that provides structural support for the second dielectric layer. Turning to Figure 1, a first dielectric layer 101 is disposed over a substrate 100 and a second dielectric layer 102 is disposed over the first dielectric layer 101. The first dielectric layer 101 provides structural support for the second dielectric layer and has good thermal conduction properties. The second dielectric layer is a low dielectric constant (low-k) material The multi-layer dielectric structure shown in Figure 1 aids in the reduction in the parasitic capacitance between conductive elements 103.

In the exemplary embodiment shown in Figure 1, the present invention reduces CL-L between conductive elements 103 which may be metal rurmers. The first dielectric layer 101 may be referred to as the structural layer and the second dielectric layer 102 may be referred to as the low-k dielectric layer. In the exemplary embodiments shown in Figures 2(a)-(e), 3 and 4, dual damascene structures with reduced line-to-line capacitance are disclosed. In embodiments drawn to dual damascene structures, the first dielectric layer may be referred to as the via dielectric because this is the layer where a via is formed; and the second dielectric layer in these embodiments may be refeffed to as the trench dielectric because a trench is formed in this layer. Finally, the exemplary fabrication techniques for forming the structure shown in Figure I are substantially the same as those used in connection with the exemplary embodiments discussed below.

Turning to Fig. 2 (a), the substrate 201 has conductive elements 202 disposed thereover by standard technique. The substrate may be a semiconductor such as silicon, GaAs, or SiGe; or a dielectric material as well as other materials used in fabricating integrated circuits. Tlie via layer 203 is formed over the substrate 201 by conventional deposition techniques and has an exemplary thickness of 600 to 900 ran. Illustratively, this layer is formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD). The via dielectric material is chosen for its mechanical, thermal and plasma etching characteristics. To this end, this layer provides mechanical stability/rigidity to the trench layer 204. The via layer 203 may dissipate heat better than the trench dielectric material and etches at a different rate than the trench dielectric as discussed in detail below. Materials having a Young's modulus in the range of about 60 GPa to 120 GPa. and a thermal conductivity in the range of about 9.0 mW/cm-K to 17.0 mW/cm-K may be used as the via dielectric layer. Exemplary materials include but are not limited to silicon dioxide and fluorine doped silicon dioxide (also know as fluorosilicate glass (FSG)).

After formation of the via dielectric, the trench dielectric 204 is formed over the via dielectric in an exemplary thickness of 300 to 800 rim. The trench dielectric layer may be deposited by a standard spin-on technique, as well as by PECVD. Exemplary trench dielectric materials include: a low dielectric organic polymer (e.g. S]ILKO,a registered trademark of Dow Chemical Company); hybrido organo, siloxane polymer (e.g. Allied Signal Corporation tradename HOSP); nanoporous silicate glass (e. g. Allied Signal Corporation tradename Nanoglass); and organo silicate glass (e.g. Applied Materials Corporation tradename Black Diamond or Novellus Corporation tradename COREL. In the exemplary embodiment, the dielectric constant of layer 204 is less than the dielectric constant of layer 203. Illustratively, trench layer 204 may have a dielectric constant on the order of 2.0 to 3.7. However, it is within the purview of the present invention to use materials as the trench dielectric 203 having a dielectric constant of less than 2.0. The low-k trench dielectric reduces the overall dielectric constant of the interlayer dielectric (ILD) thereby reducing the line-to-line capacitance as is desired.

4 Turning to Fig. 2 (b) the via 205 is shown. In the exemplary embodiment, etching of the via 205 is carried out by reactive ion etching. The etch may be done by known techniques to achieve a vertical etch profile. The via etch process is terminated at or slightly before a bottom passivation. layer (not shown) located over the conductive element 202. Finally, conventional chemistries used to etch silicon dioxide and FSG are used in the via etch step.

A layer of photoresist 206 is used to define the trench, as is shown in Fig. 2 (c). Turning to Fig. 2 (d)the trench 207 is shown having been etched illustratively by reactive ion etching using processes which provide a high degree of selectivity between the trench layer 204 and via layer 203. Accordingly, the complexity of having an etch stop layer as is needed by prior techniques may be foregone.

Illustrative etch chemistries for some of the exemplary materials are as follows. In the example when a purely organic material such as SILK@ is used for the trench layer 204 and the via layer is SiO2 or FSG, the use of etch chemistries cont i i g oxygen and hydrogen (but not fluorine) will produce etch selectivities on the order of 20: 1. When the trench layer 204 is nanoglass (porous Si02) and the layer 203 is Si02 or FSG, conventional oxide etch chemistries such as CHF3/CF4 or C4Fs/CO produce etch selectivities on the order of 4:1 between layers 204 and 203.

As a result of the etch selectivity improved control of the trench depth within a wafer and from wafer-to-wafer results. Furthermore, the etching of the trench 207 may be carried out to achieve a vertical etch profile. Finally, the trench etch may employ an endpoint detection technique known to those skilled in the art to terminate the etch just after reaching the via. The resulting dual damascene structure is shown in Figure 2 (e) after the via 205 and trench 207 are filled with a conductor 208 by standard technique.

Turning to Fig. 3 and Fig. 4, alternative fabrication techniques within the purview of the present invention are shown. The materials and processes used to effect the alternative embodiment shown in Fig. 3 are substantially identical to that discussed in connection with the structure in which the full via is fabricated first. Fig. 3 shows an exemplary embodiment of the invention of the present disclosure in which a trench is fabricated through the selectivity between layers 203 and 204. After the etching of the trench layer 204 to form the trench 207, a via photoresist 301 is disposed and a M via 205 is etched. In the structure shown in Fig. 4, a partial via is formed as is shown at 40 1. Thereafter, a trench photoresist 402 is disposed over the trench layer 204. A plasma etching step is thereafter carried out by standard technique resulting in a full via and trench being fabricated.

The invention having been described in detail, it is clear that modifications and variations are within the purview of one of ordinary skill in the art having the benefit of present invention. To the extent that such modifications are within the teaching of the present disclosure drawn to an integrated circuit and its method of fabrication having a reduce ELD dielectric constant through the use of a multi-layer dielectric structu re such are within the purview of one of ordinary skill in the art.

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Claims

What is Claimed:

1 1. An integrated circuit, comprising:

2 a multi-layer dielectric disposed over a substrate, said multi-layer 3 dielectric further comprising a low-k layer disposed over a structural layer.

1
2. An integrated circuit as recited in claim 1, wherein said low-I layer is 2 disposed between at least two conductive elements.

1
3. An integrated circuit as recited in claim 1, wherein said low-k layer 2 has a dielectric constant in the range of 2.0 to 3.7.

1
4. An integrated circuit as recited in claim 1, wherein said low-k layer 2 has a dielectric constant less than 2.0.

1
5. An integrated circuit as recited in claim 1, wherein said low-k layer 2 is chosen from the group consisting of SILK@, HOSP, Nanoglass and Black Diamond.

1
6. An integrated circuit as recited in claim 1, wherein said structural 2 layer is chosen from the group consisting of Si% and fluorine doped silicon oxide.

1
7. An integrated circuit as recited in claim 1, wherein said structural 2 layer has a Young's modulus in the range of 60 GPa to 120 GPa.

1
8. An integrated circuit, comprising:

2 a substrate; 3 a layer disposed over said substrate and having a via therein; 4 a low-k layer disposed on said layer; and a trench disposed in said low-k layer.

1
9. A integrated circuit as recited in claim 8, wherein said low-k layer 2 has a dielectric constant in the range 2.0 to 3.7.

1
10. An integrated circuit as recited in claim 8, wherein said low-k layer 2 has a dielectric constant less than 2.0.

1
11. An integrated circuit as recited in claim 8, wherein said low-k 2 material is chosen from the group consisting of SILKO, HOSP, Nanoglass and Black 3 Diamond.

1
12. An integrated circuit as recited in claim 8, wherein said layer is 2 chosen from the comprising of Si% and fluorine doped silicon dioxide.

1
13. An integrated circuit as recited in claim 8, wherein conductive 2 material is disposed in said via and in said trench. 1
14. An integrated circuit, comprising: 2 a multi-layer dielectric disposed over a substrate, said multi-layer 3 dielectric further comprising a low-k layer disposed over a structural layer and directly 4 on a conductive element. 1
15. An integrated circuit as recited in claim 14, wherein said low-k 2 layer is disposed between at least two conductive elements. 1
16. An integrated circuit as recited in claim 14 wherein said low-k layer 2 has a dielectric constant in range of 2.0 to 3.7. 1
17. An integrated circuit as recited in claim 14, wherein said low-k 2 layer has a dielectric constant less than 2.0. 1
18. An integrated circuit as recited in claim 14, wherein said low-k 2 layer is chosen from the group consisting of SELK0, HOSP, Nanoglass and Black 3 Diamond.

1
19. An integrated circuit as recited in claim 14, wherein said structural 2 layer is chosen from the group consisting Of Si02 and fluorine doped silicon dioAide. 1
20. An integrated circuit as recited in claim 14, wherein said structural 2 layer has a Young's modulus in the range of 60 GPa to 120 GPa.

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