KR970054601A - 반도체 디바이스 제조공정의 금속층 패터닝(Patterning) 방법 - Google Patents

반도체 디바이스 제조공정의 금속층 패터닝(Patterning) 방법 Download PDF

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Publication number
KR970054601A
KR970054601A KR1019950058235A KR19950058235A KR970054601A KR 970054601 A KR970054601 A KR 970054601A KR 1019950058235 A KR1019950058235 A KR 1019950058235A KR 19950058235 A KR19950058235 A KR 19950058235A KR 970054601 A KR970054601 A KR 970054601A
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KR
South Korea
Prior art keywords
metal layer
manufacturing process
semiconductor device
device manufacturing
patterning method
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Application number
KR1019950058235A
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English (en)
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KR100368985B1 (ko
Inventor
이복형
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문정환
Lg 반도체 주식회사
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Priority to KR1019950058235A priority Critical patent/KR100368985B1/ko
Publication of KR970054601A publication Critical patent/KR970054601A/ko
Application granted granted Critical
Publication of KR100368985B1 publication Critical patent/KR100368985B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • G03F7/422Stripping or agents therefor using liquids only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 디바이스 제조공정의 금속층 패터닝 방법에 관한 것으로써, 반도체 기판 상에 형성된 금속층 위에 포토레지스트 마스크를 형성하고, 금속층을 건식각 단계 후, 폴리머를 제거하는 단계를 실시한 다음, 포토레지스트 마스크를 제거하고, 재차 폴리머 제거하는 단계를 포함하여 이루어진다.

Description

반도체 디바이스 제조공정의 금속층 패터닝(Patterning) 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 일실시예의 반도체 디바이스 제조공정의 금속층 패터닝 방법을 설명하기 위해 도시한 공정 플로우차트(Flowchart).

Claims (2)

  1. 반도체 디바이스 제조공정의 금속층 패터닝(Patterning) 방법에 있어서, 반도체 기판 상에 형성된 금속층 위에 포토레지스트 마스크를 형성하고, 상기 금속층을 건식각한 후, 상기 포토레지스트 마스크를 제거하기 전에 건식각시에 발생된 폴러머를 먼저 제거하는 것이 특징인 반도체 디바이스 제조공정의 금속층 패터닝 방법.
  2. 제1항에 있어서, 상기 포토레지스트 마스크 제거후, 폴리머 제거 단계를 추가하는 것이 특징인 반도체 디바이스 제조공정의 금속층 패터닝 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950058235A 1995-12-27 1995-12-27 반도체디바이스제조공정의금속층패터닝방법 KR100368985B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058235A KR100368985B1 (ko) 1995-12-27 1995-12-27 반도체디바이스제조공정의금속층패터닝방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058235A KR100368985B1 (ko) 1995-12-27 1995-12-27 반도체디바이스제조공정의금속층패터닝방법

Publications (2)

Publication Number Publication Date
KR970054601A true KR970054601A (ko) 1997-07-31
KR100368985B1 KR100368985B1 (ko) 2003-03-31

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ID=37416344

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KR1019950058235A KR100368985B1 (ko) 1995-12-27 1995-12-27 반도체디바이스제조공정의금속층패터닝방법

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8741691B2 (en) 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122541A (ja) * 1993-10-25 1995-05-12 Sony Corp アルミニウム系配線の加工方法

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KR100368985B1 (ko) 2003-03-31

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