KR970030388A - 반도체 장치의 콘택홀 형성방법 - Google Patents

반도체 장치의 콘택홀 형성방법 Download PDF

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Publication number
KR970030388A
KR970030388A KR1019950043278A KR19950043278A KR970030388A KR 970030388 A KR970030388 A KR 970030388A KR 1019950043278 A KR1019950043278 A KR 1019950043278A KR 19950043278 A KR19950043278 A KR 19950043278A KR 970030388 A KR970030388 A KR 970030388A
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South Korea
Prior art keywords
insulating film
contact hole
forming
etching
maintaining
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KR1019950043278A
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English (en)
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KR100365767B1 (ko
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박희국
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김주용
현대전자산업 주식회사
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Priority to KR1019950043278A priority Critical patent/KR100365767B1/ko
Publication of KR970030388A publication Critical patent/KR970030388A/ko
Application granted granted Critical
Publication of KR100365767B1 publication Critical patent/KR100365767B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체장치의 콘택홀 형성방법에 관한 것으로, 기판상에 절연막을 형성하는 단계와, 상기 절연막상에 포토레지스트 패턴을 형성하는 단계, 기판온도를 100℃ 이하로 유지하면서 상기 포토레지스트 패턴을 마스크로 이용하여 상기 절연막을 플라즈마 식각에 의해 소정 두께만큼 식각하는 단계, 및 기판온도를 150℃ 이상으로 유지하면서 절연막의 나머지 부분을 식각하여 콘택홀을 형성하는 단계로 이루어지는 반도체장치의 콘택홀 형성방법을 제공함으로써 완만하게 경사진 콘택홀의 형성을 가능하게 하여 금속 증착시의 스텝 커버리지를 향상시킨다.

Description

반도체 장치의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 반도체장치의 콘택홀 형성방법을 도시한 공정순서도.

Claims (4)

  1. 기판상에 절연막을 형성하는 단계와, 상기 절연막상에 포토레지스트 패턴을 형성하는 단계, 기판온도를100℃ 이하로 유지하면서 상기 포토레지스트 패턴을 마스크로 이용하여 상기 절연막을 플라즈마 식각에 의해 소정두께만큼 식각하는 단계, 및 기판온도를 150℃ 이상으로 유지하면서 절연막의 나머지 부분을 식각하여 콘택홀을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 기판온도를 100℃ 이하로 유지하여 상기 절연막을 플라즈마 식각에 의해 식각하는 단계에서 플라즈마 식각시의 식각 부산물의 중합이 원활하게 이루어져 절연막의 측면이 경사지게 형성되는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 콘택홀이 윗부분이 넓은 Y자 형태로 형성되는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법.
  4. 제l항에 있어서, 상기 플라즈마 식각시 식각가스로 CF, CHF계통을 사용하는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950043278A 1995-11-23 1995-11-23 반도체장치의콘택홀형성방법 KR100365767B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950043278A KR100365767B1 (ko) 1995-11-23 1995-11-23 반도체장치의콘택홀형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043278A KR100365767B1 (ko) 1995-11-23 1995-11-23 반도체장치의콘택홀형성방법

Publications (2)

Publication Number Publication Date
KR970030388A true KR970030388A (ko) 1997-06-26
KR100365767B1 KR100365767B1 (ko) 2003-03-03

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KR1019950043278A KR100365767B1 (ko) 1995-11-23 1995-11-23 반도체장치의콘택홀형성방법

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Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04199849A (ja) * 1990-11-29 1992-07-21 Nec Corp 半導体装置の製造方法

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KR100365767B1 (ko) 2003-03-03

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