KR970012193A - 데이타 처리 시스템을 초기화(initializing) 하기 위한 방법과 회로 - Google Patents
데이타 처리 시스템을 초기화(initializing) 하기 위한 방법과 회로 Download PDFInfo
- Publication number
- KR970012193A KR970012193A KR1019960036638A KR19960036638A KR970012193A KR 970012193 A KR970012193 A KR 970012193A KR 1019960036638 A KR1019960036638 A KR 1019960036638A KR 19960036638 A KR19960036638 A KR 19960036638A KR 970012193 A KR970012193 A KR 970012193A
- Authority
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- South Korea
- Prior art keywords
- data processing
- signal
- receiving
- central processing
- information values
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
- G06F11/364—Software debugging by tracing the execution of the program tracing values on a bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Debugging And Monitoring (AREA)
Abstract
데이타 처리장치(3)는 리셋 연산을 위한 예의 처리 루틴이 개시되기 전에 브레이크포인트 연산을 실행한다. 외부 리셋 신호가 표명되고 계속해서 부정된 경우, 실제 리셋 예외 처리 루틴을 시작하기 전에 데이타 처리 장치 가 정지되어 있는 시간의 윈도우가 존재한다. 만일 외부 프레이크포인트 신호, BKPT가 외부개발시스템(7)에 의해 정지시간 동안 표명되면, 데이타 처리장치(3)는 하드웨어 레지스터 구성 어느 것이라도 실행될 수 있도록 목표 메모리 값을 메모리(6)에 다운 로드(down load)한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 한 실시예에 따른 데이타 처리 시스템을 나타내는 블럭도,
제2도는 제1도의 데이타 처리 시스템의 디버그 모듈의 일부를 나타내는 블럭도,
제3도는 제2도의 디버그 모듈의 브레이크포인트 회로를 나타내는 블럭도.
Claims (2)
- 데이타 처리 시스템에 있어서, 다수의 정보 값을 제공하기 위한 외부개발시스템과, 데이타 처리장치와, 브레이크포인트 신호, 리셋 신호, 그리고 상기 다수의 정보 값을 수신하기 위한 입력수단과, 상기 다수의 정보값을 수신하기 위한 상기 외부개발 시스템에 결합된 상기 입력수단을 포함하는 상기 데이타 처리장치와, 상기 브레이크포인트 신호, 상기 리셋 신호, 그리고 상디 다수의 정보 값을 수신하기 위한 상기 입력수단에 결합된 중앙처리장치와, 상기 리셋 신호가 제1논리상태에 있는 경우 정지시간 주기동안 연산을 중단시키는 상기 중앙 처리장치와, 그리고 상기 브레이크포인트 신호가 상기 정지 시간 주시동안 제2논리 상태에 있는 경우 내부 레지스터에 상기 다수의 정보 값의 일부분을 선택적으로 기억하는 상기 중앙처리장치를 포함하는 상기 데이타 처리장치를 포함하는 것을 특징으로 하는 데이타 처리 시스템.
- 데이타 처리장치를 초기화 하기 위한 방법에 있어서, 외부개발시스템으로 부터 다수의 정보를 수신하는 단계와, 입력회로에서 브레이크포인트 신호를 수신하는 단계와, 입력 회로에서 리셋 신호를 수신하는 단계와, 상기 브레이크포인트 신호와 상기 리셋 신호를 수신하기 위해 상기 입력회로에 중앙처리장을 결합하는 단계와, 상기 다수의 정보 값을 수신하기 위한 상기 외부개발시스템에 상기 중앙처리장치를 결합하는 단계와, 상기 리셋 신호가 제1논리 상태에 있는 경우, 정지시간 주기 동안 상기 중앙처리 장치의 연산을 중단시키는 단계와, 상기 브레이크포인트 신호가 정지시간 주기 동안 제2논리 상태에 있는 경우, 내부 레지스터에 상기 다수의 정보의 일부분을 선택적으로 기억하는 단계를 포함하는 것을 특징으로 하는 데이타 처리장치를 초기화 하기 위한 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/520,949 US5704034A (en) | 1995-08-30 | 1995-08-30 | Method and circuit for initializing a data processing system |
US520,949 | 1995-08-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970012193A true KR970012193A (ko) | 1997-03-29 |
KR100394897B1 KR100394897B1 (ko) | 2003-11-10 |
Family
ID=24074711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960036638A KR100394897B1 (ko) | 1995-08-30 | 1996-08-30 | 데이터처리장치및데이터처리장치제공방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5704034A (ko) |
EP (1) | EP0762277B1 (ko) |
JP (1) | JPH09128265A (ko) |
KR (1) | KR100394897B1 (ko) |
DE (1) | DE69616708T2 (ko) |
Families Citing this family (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6317803B1 (en) * | 1996-03-29 | 2001-11-13 | Intel Corporation | High-throughput interconnect having pipelined and non-pipelined bus transaction modes |
US5889981A (en) * | 1996-05-07 | 1999-03-30 | Lucent Technologies Inc. | Apparatus and method for decoding instructions marked with breakpoint codes to select breakpoint action from plurality of breakpoint actions |
US5903912A (en) * | 1996-08-14 | 1999-05-11 | Advanced Micro Devices, Inc. | Microcontroller configured to convey data corresponding to internal memory accesses externally |
US5860161A (en) * | 1996-08-14 | 1999-01-12 | Advanced Micro Devices, Inc. | Microcontroller configured to indicate internal memory accesses externally |
DE19642844C1 (de) * | 1996-10-17 | 1997-12-11 | Bosch Gmbh Robert | Schaltungsanordnung mit einem Mikroprozessor |
DE69715558T2 (de) * | 1996-10-31 | 2003-05-22 | Stmicroelectronics Ltd., Almondsbury | Mikrorechner mit Urladungsystem |
DE69715346T2 (de) * | 1996-10-31 | 2003-06-05 | Stmicroelectronics Ltd., Almondsbury | Mikrorechner mit Fehlersuchsystem |
GB9622684D0 (en) | 1996-10-31 | 1997-01-08 | Sgs Thomson Microelectronics | An integrated circuit device and method of communication therwith |
US5983017A (en) * | 1996-11-12 | 1999-11-09 | Lsi Logic Corporation | Virtual monitor debugging method and apparatus |
GB9626412D0 (en) * | 1996-12-19 | 1997-02-05 | Sgs Thomson Microelectronics | Diagnostic procedures in an integrated circuit device |
US5862148A (en) * | 1997-02-11 | 1999-01-19 | Advanced Micro Devices, Inc. | Microcontroller with improved debug capability for internal memory |
US5931956A (en) * | 1997-06-10 | 1999-08-03 | Atmel Corporation | Digital circuit using memory for monitoring signals for occurrences of predefined breakpoint conditions |
US6356960B1 (en) | 1997-10-29 | 2002-03-12 | Sgs-Thomson Microelectronics Limited | Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port |
US6167365A (en) * | 1998-02-06 | 2000-12-26 | Texas Instruments Incorporated | Method of initializing CPU for emulation |
DE69918737T2 (de) * | 1998-03-20 | 2005-09-01 | Texas Instruments Inc., Dallas | Initialisierungsverfahren eines CPU zur Emulation |
JP4335999B2 (ja) * | 1999-05-20 | 2009-09-30 | 株式会社ルネサステクノロジ | プロセッサ内蔵半導体集積回路装置 |
US6598178B1 (en) * | 1999-06-01 | 2003-07-22 | Agere Systems Inc. | Peripheral breakpoint signaler |
US7266728B1 (en) | 1999-10-01 | 2007-09-04 | Stmicroelectronics Ltd. | Circuit for monitoring information on an interconnect |
US6463553B1 (en) | 1999-10-01 | 2002-10-08 | Stmicroelectronics, Ltd. | Microcomputer debug architecture and method |
US6928073B2 (en) * | 1999-10-01 | 2005-08-09 | Stmicroelectronics Ltd. | Integrated circuit implementing packet transmission |
US6542983B1 (en) | 1999-10-01 | 2003-04-01 | Hitachi, Ltd. | Microcomputer/floating point processor interface and method |
US6859891B2 (en) * | 1999-10-01 | 2005-02-22 | Stmicroelectronics Limited | Apparatus and method for shadowing processor information |
US7260745B1 (en) | 1999-10-01 | 2007-08-21 | Stmicroelectronics Ltd. | Detection of information on an interconnect |
US6574651B1 (en) | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
US6457118B1 (en) | 1999-10-01 | 2002-09-24 | Hitachi Ltd | Method and system for selecting and using source operands in computer system instructions |
US6590907B1 (en) | 1999-10-01 | 2003-07-08 | Stmicroelectronics Ltd. | Integrated circuit with additional ports |
US6693914B1 (en) | 1999-10-01 | 2004-02-17 | Stmicroelectronics, Inc. | Arbitration mechanism for packet transmission |
US6434665B1 (en) | 1999-10-01 | 2002-08-13 | Stmicroelectronics, Inc. | Cache memory store buffer |
US7072817B1 (en) * | 1999-10-01 | 2006-07-04 | Stmicroelectronics Ltd. | Method of designing an initiator in an integrated circuit |
US6701405B1 (en) | 1999-10-01 | 2004-03-02 | Hitachi, Ltd. | DMA handshake protocol |
US6598177B1 (en) | 1999-10-01 | 2003-07-22 | Stmicroelectronics Ltd. | Monitoring error conditions in an integrated circuit |
US6732307B1 (en) | 1999-10-01 | 2004-05-04 | Hitachi, Ltd. | Apparatus and method for storing trace information |
US6826191B1 (en) | 1999-10-01 | 2004-11-30 | Stmicroelectronics Ltd. | Packets containing transaction attributes |
US7793261B1 (en) | 1999-10-01 | 2010-09-07 | Stmicroelectronics Limited | Interface for transferring debug information |
US6629207B1 (en) | 1999-10-01 | 2003-09-30 | Hitachi, Ltd. | Method for loading instructions or data into a locked way of a cache memory |
US7000078B1 (en) * | 1999-10-01 | 2006-02-14 | Stmicroelectronics Ltd. | System and method for maintaining cache coherency in a shared memory system |
US6629115B1 (en) | 1999-10-01 | 2003-09-30 | Hitachi, Ltd. | Method and apparatus for manipulating vectored data |
US6412047B2 (en) | 1999-10-01 | 2002-06-25 | Stmicroelectronics, Inc. | Coherency protocol |
US6502210B1 (en) | 1999-10-01 | 2002-12-31 | Stmicroelectronics, Ltd. | Microcomputer debug architecture and method |
US6412043B1 (en) | 1999-10-01 | 2002-06-25 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US6665816B1 (en) | 1999-10-01 | 2003-12-16 | Stmicroelectronics Limited | Data shift register |
JP2001142692A (ja) * | 1999-10-01 | 2001-05-25 | Hitachi Ltd | 2つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法 |
US6546480B1 (en) | 1999-10-01 | 2003-04-08 | Hitachi, Ltd. | Instructions for arithmetic operations on vectored data |
US6460174B1 (en) | 1999-10-01 | 2002-10-01 | Stmicroelectronics, Ltd. | Methods and models for use in designing an integrated circuit |
US6820195B1 (en) | 1999-10-01 | 2004-11-16 | Hitachi, Ltd. | Aligning load/store data with big/little endian determined rotation distance control |
US6553460B1 (en) | 1999-10-01 | 2003-04-22 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US6779145B1 (en) | 1999-10-01 | 2004-08-17 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6298394B1 (en) | 1999-10-01 | 2001-10-02 | Stmicroelectronics, Ltd. | System and method for capturing information on an interconnect in an integrated circuit |
US6615370B1 (en) | 1999-10-01 | 2003-09-02 | Hitachi, Ltd. | Circuit for storing trace information |
US6530047B1 (en) | 1999-10-01 | 2003-03-04 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6684348B1 (en) | 1999-10-01 | 2004-01-27 | Hitachi, Ltd. | Circuit for processing trace information |
US6772325B1 (en) * | 1999-10-01 | 2004-08-03 | Hitachi, Ltd. | Processor architecture and operation for exploiting improved branch control instruction |
US6408381B1 (en) | 1999-10-01 | 2002-06-18 | Hitachi, Ltd. | Mechanism for fast access to control space in a pipeline processor |
US6557119B1 (en) | 1999-10-01 | 2003-04-29 | Stmicroelectronics Limited | Microcomputer debug architecture and method |
US6601189B1 (en) | 1999-10-01 | 2003-07-29 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6349371B1 (en) | 1999-10-01 | 2002-02-19 | Stmicroelectronics Ltd. | Circuit for storing information |
US6487683B1 (en) | 1999-10-01 | 2002-11-26 | Stmicroelectronics Limited | Microcomputer debug architecture and method |
US6633971B2 (en) | 1999-10-01 | 2003-10-14 | Hitachi, Ltd. | Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline |
US6449712B1 (en) | 1999-10-01 | 2002-09-10 | Hitachi, Ltd. | Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions |
US6351803B2 (en) | 1999-10-01 | 2002-02-26 | Hitachi Ltd. | Mechanism for power efficient processing in a pipeline processor |
US6598128B1 (en) | 1999-10-01 | 2003-07-22 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US6918065B1 (en) | 1999-10-01 | 2005-07-12 | Hitachi, Ltd. | Method for compressing and decompressing trace information |
US6567932B2 (en) | 1999-10-01 | 2003-05-20 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6591369B1 (en) | 1999-10-01 | 2003-07-08 | Stmicroelectronics, Ltd. | System and method for communicating with an integrated circuit |
US6591378B1 (en) * | 2000-02-22 | 2003-07-08 | Motorola, Inc. | Debug controller in a data processor and method therefor |
US6985848B2 (en) * | 2000-03-02 | 2006-01-10 | Texas Instruments Incorporated | Obtaining and exporting on-chip data processor trace and timing information |
US7213207B2 (en) * | 2000-12-20 | 2007-05-01 | National Instruments Corporation | System and method for accessing registers of a hardware device in a graphical program |
US6718539B1 (en) * | 2000-12-22 | 2004-04-06 | Lsi Logic Corporation | Interrupt handling mechanism in translator from one instruction set to another |
US7069545B2 (en) * | 2000-12-29 | 2006-06-27 | Intel Corporation | Quantization and compression for computation reuse |
JP4021670B2 (ja) * | 2002-01-22 | 2007-12-12 | 株式会社東芝 | 半導体集積回路 |
US7441104B2 (en) * | 2002-03-30 | 2008-10-21 | Hewlett-Packard Development Company, L.P. | Parallel subword instructions with distributed results |
US7010672B2 (en) * | 2002-12-11 | 2006-03-07 | Infineon Technologies Ag | Digital processor with programmable breakpoint/watchpoint trigger generation circuit |
WO2006079962A2 (en) * | 2005-01-28 | 2006-08-03 | Nxp B.V. | Means and method for debugging |
US20070050678A1 (en) * | 2005-08-25 | 2007-03-01 | Motorola, Inc. | Apparatus for self-diagnosis and treatment of critical software flaws |
US8010774B2 (en) * | 2006-03-13 | 2011-08-30 | Arm Limited | Breakpointing on register access events or I/O port access events |
US8381192B1 (en) * | 2007-08-03 | 2013-02-19 | Google Inc. | Software testing using taint analysis and execution path alteration |
US8479014B1 (en) * | 2007-09-04 | 2013-07-02 | Guoan Hu | Symmetric key based secure microprocessor and its applications |
US8195986B2 (en) * | 2008-02-25 | 2012-06-05 | International Business Machines Corporation | Method, system and computer program product for processing error information in a system |
GB2530050B (en) * | 2014-09-10 | 2021-07-21 | Advanced Risc Mach Ltd | Debugging in a data processing apparatus |
IN2015CH04519A (ko) * | 2015-08-27 | 2015-09-11 | Wipro Ltd | |
US10120740B2 (en) | 2016-03-22 | 2018-11-06 | Micron Technology, Inc. | Apparatus and methods for debugging on a memory device |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3937938A (en) * | 1974-06-19 | 1976-02-10 | Action Communication Systems, Inc. | Method and apparatus for assisting in debugging of a digital computer program |
US4080650A (en) * | 1976-07-28 | 1978-03-21 | Bell Telephone Laboratories, Incorporated | Facilitating return from an on-line debugging program to a target program breakpoint |
US4338660A (en) * | 1979-04-13 | 1982-07-06 | Relational Memory Systems, Inc. | Relational break signal generating device |
US4675646A (en) * | 1983-09-29 | 1987-06-23 | Tandem Computers Incorporated | RAM based multiple breakpoint logic |
US4635193A (en) * | 1984-06-27 | 1987-01-06 | Motorola, Inc. | Data processor having selective breakpoint capability with minimal overhead |
US5165027A (en) * | 1986-01-24 | 1992-11-17 | Intel Corporation | Microprocessor breakpoint apparatus |
US4819234A (en) * | 1987-05-01 | 1989-04-04 | Prime Computer, Inc. | Operating system debugger |
US5179696A (en) * | 1987-07-24 | 1993-01-12 | Nec Corporation | Generator detecting internal and external ready signals for generating a bus cycle end signal for microprocessor debugging operation |
JPH0193837A (ja) * | 1987-10-05 | 1989-04-12 | Nec Corp | デバッグ用マイクロプロセッサ |
US5084814A (en) * | 1987-10-30 | 1992-01-28 | Motorola, Inc. | Data processor with development support features |
US5053949A (en) * | 1989-04-03 | 1991-10-01 | Motorola, Inc. | No-chip debug peripheral which uses externally provided instructions to control a core processing unit |
JPH03204737A (ja) * | 1990-01-08 | 1991-09-06 | Nec Corp | 信号処理プロセッサのデバッグ回路 |
JP2526690B2 (ja) * | 1990-02-27 | 1996-08-21 | 三菱電機株式会社 | プログラマブルコントロ―ラの制御方法 |
JPH03248244A (ja) * | 1990-02-27 | 1991-11-06 | Toshiba Corp | キャッシュメモリを備えたプロセッサ |
US5410685A (en) * | 1990-06-12 | 1995-04-25 | Regents Of The University Of Michigan | Non-intrinsive method and system for recovering the state of a computer system and non-intrusive debugging method and system utilizing same |
US5204864A (en) * | 1990-08-16 | 1993-04-20 | Westinghouse Electric Corp. | Multiprocessor bus debugger |
WO1992014202A1 (en) * | 1991-02-01 | 1992-08-20 | Digital Equipment Corporation | Method for testing and debugging computer programs |
US5321828A (en) * | 1991-06-07 | 1994-06-14 | Step Engineering | High speed microcomputer in-circuit emulator |
JPH06195478A (ja) * | 1992-07-21 | 1994-07-15 | Advanced Micro Devicds Inc | 集積回路 |
US5359608A (en) * | 1992-11-24 | 1994-10-25 | Amdahl Corporation | Apparatus for activation and deactivation of instruction tracing through use of conditional trace field in branch instructions |
US5546562A (en) * | 1995-02-28 | 1996-08-13 | Patel; Chandresh | Method and apparatus to emulate VLSI circuits within a logic simulator |
-
1995
- 1995-08-30 US US08/520,949 patent/US5704034A/en not_active Expired - Lifetime
-
1996
- 1996-08-22 EP EP96113468A patent/EP0762277B1/en not_active Expired - Lifetime
- 1996-08-22 DE DE69616708T patent/DE69616708T2/de not_active Expired - Fee Related
- 1996-08-22 JP JP8239892A patent/JPH09128265A/ja active Pending
- 1996-08-30 KR KR1019960036638A patent/KR100394897B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69616708T2 (de) | 2002-08-01 |
JPH09128265A (ja) | 1997-05-16 |
DE69616708D1 (de) | 2001-12-13 |
EP0762277B1 (en) | 2001-11-07 |
US5704034A (en) | 1997-12-30 |
EP0762277A1 (en) | 1997-03-12 |
KR100394897B1 (ko) | 2003-11-10 |
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