KR970012193A - 데이타 처리 시스템을 초기화(initializing) 하기 위한 방법과 회로 - Google Patents

데이타 처리 시스템을 초기화(initializing) 하기 위한 방법과 회로 Download PDF

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KR970012193A
KR970012193A KR1019960036638A KR19960036638A KR970012193A KR 970012193 A KR970012193 A KR 970012193A KR 1019960036638 A KR1019960036638 A KR 1019960036638A KR 19960036638 A KR19960036638 A KR 19960036638A KR 970012193 A KR970012193 A KR 970012193A
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data processing
signal
receiving
central processing
information values
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KR1019960036638A
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KR100394897B1 (ko
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씨. 써셀로 죠셉
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3636Software debugging by tracing the execution of the program
    • G06F11/364Software debugging by tracing the execution of the program tracing values on a bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

데이타 처리장치(3)는 리셋 연산을 위한 예의 처리 루틴이 개시되기 전에 브레이크포인트 연산을 실행한다. 외부 리셋 신호가 표명되고 계속해서 부정된 경우, 실제 리셋 예외 처리 루틴을 시작하기 전에 데이타 처리 장치 가 정지되어 있는 시간의 윈도우가 존재한다. 만일 외부 프레이크포인트 신호, BKPT가 외부개발시스템(7)에 의해 정지시간 동안 표명되면, 데이타 처리장치(3)는 하드웨어 레지스터 구성 어느 것이라도 실행될 수 있도록 목표 메모리 값을 메모리(6)에 다운 로드(down load)한다.

Description

데이타 처리 시스템을 초기화(initializing)하기 위한 방법과 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 한 실시예에 따른 데이타 처리 시스템을 나타내는 블럭도,
제2도는 제1도의 데이타 처리 시스템의 디버그 모듈의 일부를 나타내는 블럭도,
제3도는 제2도의 디버그 모듈의 브레이크포인트 회로를 나타내는 블럭도.

Claims (2)

  1. 데이타 처리 시스템에 있어서, 다수의 정보 값을 제공하기 위한 외부개발시스템과, 데이타 처리장치와, 브레이크포인트 신호, 리셋 신호, 그리고 상기 다수의 정보 값을 수신하기 위한 입력수단과, 상기 다수의 정보값을 수신하기 위한 상기 외부개발 시스템에 결합된 상기 입력수단을 포함하는 상기 데이타 처리장치와, 상기 브레이크포인트 신호, 상기 리셋 신호, 그리고 상디 다수의 정보 값을 수신하기 위한 상기 입력수단에 결합된 중앙처리장치와, 상기 리셋 신호가 제1논리상태에 있는 경우 정지시간 주기동안 연산을 중단시키는 상기 중앙 처리장치와, 그리고 상기 브레이크포인트 신호가 상기 정지 시간 주시동안 제2논리 상태에 있는 경우 내부 레지스터에 상기 다수의 정보 값의 일부분을 선택적으로 기억하는 상기 중앙처리장치를 포함하는 상기 데이타 처리장치를 포함하는 것을 특징으로 하는 데이타 처리 시스템.
  2. 데이타 처리장치를 초기화 하기 위한 방법에 있어서, 외부개발시스템으로 부터 다수의 정보를 수신하는 단계와, 입력회로에서 브레이크포인트 신호를 수신하는 단계와, 입력 회로에서 리셋 신호를 수신하는 단계와, 상기 브레이크포인트 신호와 상기 리셋 신호를 수신하기 위해 상기 입력회로에 중앙처리장을 결합하는 단계와, 상기 다수의 정보 값을 수신하기 위한 상기 외부개발시스템에 상기 중앙처리장치를 결합하는 단계와, 상기 리셋 신호가 제1논리 상태에 있는 경우, 정지시간 주기 동안 상기 중앙처리 장치의 연산을 중단시키는 단계와, 상기 브레이크포인트 신호가 정지시간 주기 동안 제2논리 상태에 있는 경우, 내부 레지스터에 상기 다수의 정보의 일부분을 선택적으로 기억하는 단계를 포함하는 것을 특징으로 하는 데이타 처리장치를 초기화 하기 위한 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960036638A 1995-08-30 1996-08-30 데이터처리장치및데이터처리장치제공방법 KR100394897B1 (ko)

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US08/520,949 US5704034A (en) 1995-08-30 1995-08-30 Method and circuit for initializing a data processing system
US520,949 1995-08-30

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KR100394897B1 KR100394897B1 (ko) 2003-11-10

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US (1) US5704034A (ko)
EP (1) EP0762277B1 (ko)
JP (1) JPH09128265A (ko)
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DE (1) DE69616708T2 (ko)

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DE69616708T2 (de) 2002-08-01
JPH09128265A (ja) 1997-05-16
DE69616708D1 (de) 2001-12-13
EP0762277B1 (en) 2001-11-07
US5704034A (en) 1997-12-30
EP0762277A1 (en) 1997-03-12
KR100394897B1 (ko) 2003-11-10

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