KR960702182A - 반도체 칩을 지지하기 위한 받침대 리드 프레임(a pedestal lead frame for supporting a semiconductor chip) - Google Patents
반도체 칩을 지지하기 위한 받침대 리드 프레임(a pedestal lead frame for supporting a semiconductor chip)Info
- Publication number
- KR960702182A KR960702182A KR1019950704208A KR19950704208A KR960702182A KR 960702182 A KR960702182 A KR 960702182A KR 1019950704208 A KR1019950704208 A KR 1019950704208A KR 19950704208 A KR19950704208 A KR 19950704208A KR 960702182 A KR960702182 A KR 960702182A
- Authority
- KR
- South Korea
- Prior art keywords
- pedestal
- lead frame
- layer
- substrate
- disposed
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 title claims abstract 27
- 239000000758 substrate Substances 0.000 claims abstract 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract 4
- 239000010703 silicon Substances 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims 6
- 239000012535 impurity Substances 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 2
- 238000010292 electrical insulation Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000003287 optical effect Effects 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
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- H01L23/495—Lead-frames or other flat leads
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- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
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Abstract
리드 프레임(34)상에 설치된 광학 트리거링 실리콘 제어 정류기(SCR)소자(21), SCR소자는 음극 층(24), 광학 게이트 또는 제어 층(23), 및 반도체 기판에 형성된 양극 층(31)을 포함한다. 소자는 리드 프레임에 형성된 받침대(33)에 접합된다. 리드 프레임에 소자를 접속하기 위하여, 접합물은 양극 층상에 증착되고 접착물은 리드 프레임 상의 받침대에 양극 층을 고정한다. 받침대는 리드 프레임에서 함몰부(35)를 에칭 또는 스탬핑하여 형성될 수 있다. 소자는 소자의 가장 자리가 함몰부에 인접하여 배치되고, 리드 프레임으로부터 간격이 벌어지도록 받침대상의 중앙에 배치된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 관하여 제조된 반도체 소자 일부분의 단면도.
Claims (19)
- 상승된 받침대(33)를 가지는 리드 프레임(34); 제1표면 및 반대측 가장자리를 가지는 반도체 기판(22); 제1표면에 배치된 도핑된 불순의 층(31); 및 상기 가장 자리가 전기 절연을 제공하기 위하여 상기 리드 프레임으로부터 간격을 가지도록 도핑된 불순물의 상기 층에 고정되고 상기 받침대 위로 연장하는 상기 가장 자리를 가지는 상기 받침대 상에 설치된 저항 접속부(36)를 포함하는 것을 특징으로 하는 반도체 소자.
- 제1항에 있어서, 상기 리드 프레임의 표면의 함몰부(35)는 상기 받침대를 형성하는 것을 특징으로 하는 반도체 소자.
- 제2항에 있어서, 상기 가장 자리는 인접한 상기 함몰부에 배치되는 것을 특징으로 하는 반도체 소자.
- 제3항에 있어서, 상기 층 및 상기 기판은 반대로 도핑된 것을 특징으로 하는 반도체 소자.
- 상승된 받침대(33)를 가지는 리드 프레임(34); 제1 및 제2반대의 표면과 반대 측면의 상기 가장 자리를 가지는 반도체 기판(22); 상기 기판의 상기 제1표면에서 배치된 도핑된 불순물의 제1층(31); 서로 반대로 도핑되고, 상기 기판의 상기 제2표면에 배치된 도핑된 불순물의 제2 및 제3층(23,24); 및 상기 측면 가장 자리가 상기 받침대 위로 연장하고 상기 가장 자리가 전기 절연을 제공하기 위하여 상기 리드 프레임으로부터 간격을 가지도록 상기 제1층에 고정되고 상기 받침대에 접속되는 저항 접속부(36)를 포함하는 것을 특징으로 하는 반도체 소자.
- 제5항에 있어서, 상기 리드 프레임의 표면의 함몰부(35)는 상기 받침대를 형성하는 것을 특징으로 하는 반도체 소자.
- 제6항에 있어서, 상기 가장 자리는 인접한 상기 함몰부에 배치되는 것을 특징으로 하는 반도체 소자.
- 제7항에 있어서, 상기 제1층 및 상기 기판은 반대로 도핑되는 것을 특징으로 하는 반도체 소자.
- 상부 표면, 하부 표면 및 반대측 가장 자리를 가지는 반도체 기판(22); 상기 기판의 상부 표면에 배치된 제어 층(23); 상기 제어 층의 상부 표면에 배치된 음극 층(24); 상기 음극 층에 고정된 음극 접속부(26); 상기 기판의 하부 표면에 배치된 양극 층(31); 상기 양극 층상에 증착된 양극 접속부(36); 및 상승된 받침대(33)를가지는 리드 프레임(34)을 포함하고, 상기 양극 접속부가 상기 받침대 위로 연장하는 상기 측면 가장 자리를 가지는 상기 받침대상에 고정되고 상기 리드 프레임으로부터 간격을 가지는 것을 특징으로 하는 실리콘 제어정류기(SCR)소자.
- 제9항에 있어서, 상기 받침대는 상기 리드 프레임의 표면에 배치된 함몰부(35)에 의해 형성된 상승된 부분을 포함하는 것을 특징으로 하는 실리콘 제어 정류기(SCR)소자.
- 제10항에 있어서, 상기 양극 접속부 및 상기 측면 가장 자리는 상기 함몰부에 인접하여 배치되는 것을 특징으로 하는 실리콘 제어 정류기(SCR)소자.
- 반대의 측면 가장 자리를 가지는 반도체 기판을 제공하는 단계; 상기 가장 자리 사이의 상기 기판의 표면으로 한층의 도핑된 불순물을 확산하는 단계; 리프 프레임의 표면상에 받침대를 형성하는 단계; 및 상기 측면 가장 자리가 상기 받침대위로 연장하고 상기 리드 프레임으로부터 간격이 멀어지도록 상기 층 및 상기 받침대 사이에 증착된 저항 접속부를 가지는 상기 받침대 상에 상기 기판을 설치하는 단계를 포함하는 것을 특징으로 하는 반도체 칩 제조 방법.
- 제12항에 있어서, 상기 받침대를 형성하는 단계는 상기 리드 프레임의 표면에서 함몰부를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 칩 제조 방법.
- 제13항에 있어서, 상기 함몰부는 상기 리드 프레임의 상기 표면에 스탬핑되는 것을 특징으로 하는 반도체 칩 제조 방법.
- 제13항에 있어서, 상기 함몰부는 상기 리드 프레임의 상기 표면에서 에칭되는 것을 특징으로 하는 반도체 칩 제조 방법.
- 상부 표면, 하부 표면 및 반대의 측면 가장 자리를 가지는 N형태 기판을 제공하는 단계; 상기 표면의 상부 표면으로 제1P+ 층을 확산하는 단계; 상기 P+ 층의 일부분상에 투사성의 산화물 층을 형성하는 단계; 상기 N+ 층상에 음극 접속부를 증착하는 단계; 상기 기판의 상기 하부 표면으로 제2P+ 층을 확산하는 단계; 상기 제2P+ 층상에 양극 접속부를 증착시키는 단계; 리드 프레임의 상기 표면 상에 받침대를 형성하는 단계; 및 상기 가장 자리가 상기 받침대 위로 연장하고 상기 리드 프레임으로부터 간격이 벌어지도록 상기 받침대에 고정된 상기 양극 접속부를 가지는 상기 받침대 상에 상기 기판을 설치하는 단계를 포함하는 것을 특징으로 하는 광학 트리거링 실리콘 제어 정류기(SCR)소자 제조 방법.
- 제16항에 있어서, 상기 받침대를 형성하는 단계는 상기 리드 프레임의 표면에 함몰부를 형성하는 단계를 포함하는 것을 특징으로 하는 광학 트리거링 실리콘 제어 정류기(SCR)소자 제조 방법.
- 제17항에 있어서, 상기 함몰부는 상기 리드 프레임의 상기 표면에 스탬핑되는 것을 특징으로 하는 광학트리거링 실리콘 제어 정류기(SCR)소자 제조 방법.
- 제17항에 있어서, 상기 함몰부는 상기 리드 프레임의 상기 표면에서 에칭되는 것을 특징으로 하는 광학트리거링 실리콘 제어 정류기(SCR)소자 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4082993A | 1993-03-31 | 1993-03-31 | |
US08/040829 | 1993-03-31 | ||
US08/040,829 | 1993-03-31 | ||
PCT/US1994/003555 WO1994023454A1 (en) | 1993-03-31 | 1994-03-31 | A pedestal lead frame for supporting a semiconductor chip |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960702182A true KR960702182A (ko) | 1996-03-28 |
KR100326487B1 KR100326487B1 (ko) | 2002-08-08 |
Family
ID=21913203
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Application Number | Title | Priority Date | Filing Date |
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KR1019950704208A KR100326487B1 (ko) | 1993-03-31 | 1994-03-31 | 반도체칩을지지하기위한받침대리드프레임 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5344794A (ko) |
EP (1) | EP0692144A1 (ko) |
JP (1) | JPH08508614A (ko) |
KR (1) | KR100326487B1 (ko) |
WO (1) | WO1994023454A1 (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5445974A (en) * | 1993-03-31 | 1995-08-29 | Siemens Components, Inc. | Method of fabricating a high-voltage, vertical-trench semiconductor device |
KR100275757B1 (ko) | 1998-08-31 | 2001-01-15 | 김덕중 | 반도체 정류 소자 및 이를 제조하는 방법 |
FR2784801B1 (fr) | 1998-10-19 | 2000-12-22 | St Microelectronics Sa | Composant de puissance portant des interconnexions |
US6147397A (en) * | 1999-12-28 | 2000-11-14 | Maxim Integrated Products | Stress isolated integrated circuit and method for making |
DE10339487B4 (de) * | 2003-08-27 | 2007-03-15 | Infineon Technologies Ag | Verfahren zum Aufbringen eines Halbleiterchips auf einen Träger |
US8074622B2 (en) | 2005-01-25 | 2011-12-13 | Borgwarner, Inc. | Control and interconnection system for an apparatus |
US7274089B2 (en) * | 2005-09-19 | 2007-09-25 | Stats Chippac Ltd. | Integrated circuit package system with adhesive restraint |
US8536689B2 (en) * | 2005-10-03 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit package system with multi-surface die attach pad |
DE102014115770B4 (de) | 2014-10-30 | 2018-03-29 | Infineon Technologies Ag | Verfahren zur verbindung eines substrats |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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US3902189A (en) * | 1974-04-10 | 1975-08-26 | Hunt Electronics | Prefabricated article and methods of maintaining the orientation of parts being bonded thereto |
US3928093A (en) * | 1974-06-03 | 1975-12-23 | Northern Electric Co | Method for making a bi-directional solid state device |
JPS55115364A (en) * | 1979-02-28 | 1980-09-05 | Nec Corp | Manufacturing method of semiconductor device |
JPS5835953A (ja) * | 1981-08-28 | 1983-03-02 | Hitachi Ltd | 半導体装置 |
JPS5878173A (ja) * | 1981-11-04 | 1983-05-11 | Seiko Epson Corp | 光印写装置 |
JPS6279669A (ja) * | 1985-10-03 | 1987-04-13 | Mitsubishi Electric Corp | 半導体装置 |
US4914045A (en) * | 1985-12-19 | 1990-04-03 | Teccor Electronics, Inc. | Method of fabricating packaged TRIAC and trigger switch |
JPS6373544A (ja) * | 1986-09-16 | 1988-04-04 | Matsushita Electronics Corp | リ−ドフレ−ム |
JPS63120431A (ja) * | 1986-11-10 | 1988-05-24 | Nec Corp | 電力用半導体装置 |
JPS63318761A (ja) * | 1987-06-22 | 1988-12-27 | Mitsubishi Electric Corp | 電力用半導体装置 |
JPS6431447A (en) * | 1987-07-27 | 1989-02-01 | Nec Corp | Power semiconductor device |
JPH01115127A (ja) * | 1987-10-28 | 1989-05-08 | Mitsubishi Electric Corp | 半導体装置 |
JPH027472A (ja) * | 1988-05-23 | 1990-01-11 | Mitsubishi Electric Corp | 半導体装置 |
JPH0671062B2 (ja) * | 1989-08-30 | 1994-09-07 | 株式会社東芝 | 樹脂封止型半導体装置 |
JPH07118534B2 (ja) * | 1990-02-22 | 1995-12-18 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5229327A (en) * | 1990-06-12 | 1993-07-20 | Micron Technology, Inc. | Process for manufacturing semiconductor device structures cooled by Peltier junctions and electrical interconnect assemblies therefor |
DE9114268U1 (de) * | 1991-11-15 | 1992-01-09 | Siemens AG, 8000 München | Hochspannungs-Isolierscheibe |
-
1993
- 1993-09-29 US US08/128,424 patent/US5344794A/en not_active Expired - Lifetime
-
1994
- 1994-03-31 KR KR1019950704208A patent/KR100326487B1/ko not_active IP Right Cessation
- 1994-03-31 EP EP94912918A patent/EP0692144A1/en not_active Ceased
- 1994-03-31 JP JP6522383A patent/JPH08508614A/ja not_active Ceased
- 1994-03-31 WO PCT/US1994/003555 patent/WO1994023454A1/en not_active Application Discontinuation
- 1994-12-13 US US08/355,452 patent/US5506425A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5344794A (en) | 1994-09-06 |
WO1994023454A1 (en) | 1994-10-13 |
KR100326487B1 (ko) | 2002-08-08 |
JPH08508614A (ja) | 1996-09-10 |
US5506425A (en) | 1996-04-09 |
EP0692144A1 (en) | 1996-01-17 |
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