KR960702172A - 수직 접속된 반도체 부품을 형성하기 위한 방법(process for producing vertically connected semiconductor components) - Google Patents

수직 접속된 반도체 부품을 형성하기 위한 방법(process for producing vertically connected semiconductor components)

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KR960702172A
KR960702172A KR1019950704861A KR19950704861A KR960702172A KR 960702172 A KR960702172 A KR 960702172A KR 1019950704861 A KR1019950704861 A KR 1019950704861A KR 19950704861 A KR19950704861 A KR 19950704861A KR 960702172 A KR960702172 A KR 960702172A
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semiconductor component
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에메리히 베르타크놀리
헬무트 클로제
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알베르트 발도로프, 룰프 옴케
자멘스 악티엔게젤샤프트
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

제2부품의 금속 접촉부(4')에 제1부품 금속 접촉부(4)를 접속하기 위한 수직 접촉을 만드는 접촉 구조를 가지는 부품을 형성하기 위한 가공 방법에서, 기판(1)은 수직, 전도 접속을 위해 제공된 영역에서 상부로 부터 시작하여 에칭 아웃되고, 이 리세스는 상기 금속(9)이 금속 접촉부(4)의 표면에 접속되도록 금속(9)으로 채워지고, 기판(1)의 후방 부분은 상기 후방 부분 넘어 돌출하고, 낮은 용융점을 가지는 금속, 예를들어 Auln으로 이루어진 금속화 층(9)은 제2부품의 금속 접촉부(4')에 적용되고, 상기 제2부품의 표면은 평면 층(17)이 제공되고, 두 개의 부품은 서로에 대해 수직으로 배열되고 영구적인 접촉부는 다른 것에 가압 및 가열에 의해 제1부품의 금속(9) 및 제2부품의 금속화 층(19) 사이에 생성된다.

Description

수직 접속된 반도체 부품을 형성하기 위한 방법(PROCESS FOR PRODUCING VERTICALLY CONNECTED SEMICONDUCTOR COMPONENTS)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1 내지 5도는 다른 단계의 생성 방법후에 본 발명에 따라 형성된 부품의 단면도.
제6 및 7도는 다른 단계의 생성 방법후에 먼저 부품과 접촉을 이루는 추가의 반도체 부품의 단면도.
제8도는 접촉부가 본 발명에 따라 수직으로 이루어진 것 사이의 두 부품의 단면도.

Claims (4)

  1. 추가의 반도체 부품과 수직 접촉을 형성하기 위해 접촉 구조를 가지는 반도체 부품을 형성하기 위한 방법에 있어서, 반도체 재료로 이루어지고 접촉이 이루어지도록 하는 접촉 층, 또는 금속 접촉부(4) 또는 전도트랙을 가지는 층 구조가 기판(1)상에 형성되는 제1단계; 마스크를 사용하여, 수직 리세스(10)가 상기 층 구조가 제공된 측면으로 부터 시작하여 추후의 제4단계를 위해 충분한 깊이로 상기 기판(1)으로 에칭되는 제2단계; 금속(9)이 상기 리세스(10) 및 반도체 재료로 이루어지고 접촉이 이루어진 접촉 층, 또는 금속 접촉부(4) 또는 전도체 트랙의 표면에 증착되고, 그 결과 상기 리세스(10)에 인도된 상기 금속(9)의 부분은 상기 표면에 증착딘 상기 금속(9)의 부분에 전기 전도 접속되는 제3단계; 및 층 구조가 반대인 기판(1)의 측면은 리세스(10)에서 금속(9)이 기판의 상기 측면 넘어 돌출할때까지 제거되는 제4단계를 포함하는 것을 특징으로 하는 반도체부품을 헝성하기 위한 방법.
  2. 접촉이 수직 및 전기 전도적으로 이루어진 것 사이에 반도체 부품을 형성하기 위한 방법에 있어서, 제1항에 따른 방법에 의한 제1반도체 부품 및 상기 제1반도체 부품과 수직 접촉하며 반도체 재료로 이루어지고 접촉이 이루어지도록 하는 접촉 층, 또는 금속 접촉부(4'), 또는 전도 트랙을 포함하는 층 구조를 가지는 제2부품이 형성되는 제1단계; 마스크를 사용하여, 제1반도체 부품과 접촉하기 위해 제공되는 영역까지, 전도체 트랙이 반도체 재료로 이루어진 상기 접촉 층 또는 상기 금속 접촉부(4') 또는 상기 전도 트랙에 적용된 용융점보다 금속으로 이루어진 금속화 층이 낮은 용융점을 가지는 제2단계; 두 개의 반도체 부품은 제1반도체 부품의 기판(1)에서 리세스(10)의 바깥으로 돌출하는 금속이 제2반도체 부품의 금속화 층(19)의 영역상에 배치되고, 접촉을 제공하는 방식으로 상호간의 위에 배열되는 제3단계; 및 제1반도체 부품의 금속(9)과 영구적인 전기 전도 접촉은 상기 금속화 층(19)을 가열함으로써 생성되는 제4단계를 포함하는 것을 특징으로 하는 반도체 부품을 형성하기 위한 방법.
  3. 제2항에 있어서, 텅스텐은 제1반도체 부품의 기판(1)에서 리세스(10)를 통하여 돌출하는 금속(9)을 위하여 사용되고, Auln은 제2반도체 부품 중 보다 낮은 용융점을 가지며 금속화 층(19)을 위하여 사용되는 것을 특징으로 하는 반도체 부품을 형성하기 위한 방법.
  4. 제1 내지 3항에 있어서, 반도체 부품이 실리콘을 사용하여 형성되는 것을 특징으로 하는 반도체 부품을 형성하기 위한 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950704861A 1993-05-05 1994-05-02 수직접속된반도체부품을형성하기위한방법 KR100294747B1 (ko)

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Application Number Priority Date Filing Date Title
DE4314907A DE4314907C1 (de) 1993-05-05 1993-05-05 Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
DEP4314907.3 1993-05-05
PCT/DE1994/000486 WO1994025981A1 (de) 1993-05-05 1994-05-02 Herstellungsverfahren für vertikal kontaktierte halbleiterbauelemente

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KR960702172A true KR960702172A (ko) 1996-03-28
KR100294747B1 KR100294747B1 (ko) 2001-10-24

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US (1) US5767001A (ko)
EP (1) EP0698288B1 (ko)
JP (1) JPH08510360A (ko)
KR (1) KR100294747B1 (ko)
DE (2) DE4314907C1 (ko)
WO (1) WO1994025981A1 (ko)

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EP0698288B1 (de) 1998-08-05
KR100294747B1 (ko) 2001-10-24
EP0698288A1 (de) 1996-02-28
US5767001A (en) 1998-06-16
DE59406621D1 (de) 1998-09-10
JPH08510360A (ja) 1996-10-29
WO1994025981A1 (de) 1994-11-10
DE4314907C1 (de) 1994-08-25

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