KR920018848A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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Publication number
KR920018848A
KR920018848A KR1019920004317A KR920004317A KR920018848A KR 920018848 A KR920018848 A KR 920018848A KR 1019920004317 A KR1019920004317 A KR 1019920004317A KR 920004317 A KR920004317 A KR 920004317A KR 920018848 A KR920018848 A KR 920018848A
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KR
South Korea
Prior art keywords
active layer
semiconductor device
laminating
electrically conductive
opening
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KR1019920004317A
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English (en)
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KR100237096B1 (ko
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데 브루인 레엔데르트
Original Assignee
프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
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Publication of KR920018848A publication Critical patent/KR920018848A/ko
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Publication of KR100237096B1 publication Critical patent/KR100237096B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)

Abstract

내용 없음

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1 내지 5도는 본 발명에 따른 방법을 예시하기 위한 반도체 몸체 부분의 단면도.

Claims (9)

  1. 반도체 장치를 제조하는 방법에 있어서, 상기 방법이 절연층 밑에 있는 영역의 노출된 표면 구역을 경계로 하는 절연 재료의 측벽을 한정하는 개구를 형성하는 절연층을 포함하는 표면구조를 주요 표면에서 갖는 반도체 몸체를 제공하고, 개구의 측벽 및 노출된 표면 구역상에서 활성층을 제공하고, 밑에 있는 영역과 전기적인 접촉에서의 개구에서 전기적으로 도전적인 영역을 형성하기 위해 활성층상에서 전기적으로 도전적인 재료를 적층하고, 측벽상의 활성층 재료가 노출된 표면 구역상에서 활성층 재료와 다른 특성을 갖도록 하기 위해 활성층을 제공하고 전기적으로 도전적인 재료를 적층하기 전에 개구의 측벽으로부터 활성층 재료를 제거하기 위해 활성층을 선택적으로 에칭하는 것을 특징으로 하는 반도체 장치 제조방법.
  2. 제1항에 있어서, 절연층에 대해 활성층을 적층하고 절연층의 상부 표면으로부터 활성층을 선택적으로 제거함으로써 개구의 측벽 및 노출된 표면 구역상에서 활성층을 제공하는 것을 특징으로 하는 반도체 장치 제조방법.
  3. 제2항에 있어서, 연마에 의해 상부 표면으로부터 활성층을 제거하는 것을 부가적으로 특징으로 하는 반도체 장치 제조방법.
  4. 제1항 내지 제3항 중 어느 한 항에 있어서, 스퍼터링에 의해 활성층을 제공하는 것을 부가적으로 특징으로 하는 반도체 장치 제조방법.
  5. 선항중 어느 한 항에 있어서, 티타늄－텅스텐 합금층으로써 활성층을 제공하는 것을 특징으로 하는 반도체 장치 제조방법.
  6. 제5항에 있어서, 개구의 측벽으로부터 활성층을 선택적으로 제거하기 위한 고온의 인산은 사용하는 것을 특징으로 하는 반도체 장치 제조방법.
  7. 선항중 어느 한 항에 있어서, 전기적으로 도전적인 재료를 적층하기 위해 일렉트로리스(electroless) 적층 기술을 사용하는 것을 부가적으로 특징으로 하는 반도체 제조방법.
  8. 선항중 어느 한 항에 있어서, 전기적으로 도전적인 재료로써 구리, 금 및 니켈로 구성되는 그룹으로부터 선택된 재료를 적층하는 것을 부가적으로 특징으로 하는 반도체 장치 제조방법.
  9. 제1항 내지 7항중 어느 한 항에 있어서, 전기적으로 도전적인 재료로써 텅스텐을 선택적으로 적층하는 것을 부가적으로 특징으로 하는 반도체 장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920004317A 1991-03-20 1992-03-17 반도체 장치 제조 방법 KR100237096B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9105943.6 1991-03-20
GB919105943A GB9105943D0 (en) 1991-03-20 1991-03-20 A method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
KR920018848A true KR920018848A (ko) 1992-10-22
KR100237096B1 KR100237096B1 (ko) 2000-01-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920004317A KR100237096B1 (ko) 1991-03-20 1992-03-17 반도체 장치 제조 방법

Country Status (6)

Country Link
US (1) US5240879A (ko)
EP (1) EP0504984B1 (ko)
JP (1) JP2522879B2 (ko)
KR (1) KR100237096B1 (ko)
DE (1) DE69220399T2 (ko)
GB (1) GB9105943D0 (ko)

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Also Published As

Publication number Publication date
JP2522879B2 (ja) 1996-08-07
US5240879A (en) 1993-08-31
EP0504984B1 (en) 1997-06-18
JPH0590204A (ja) 1993-04-09
EP0504984A3 (en) 1992-10-28
EP0504984A2 (en) 1992-09-23
GB9105943D0 (en) 1991-05-08
KR100237096B1 (ko) 2000-01-15
DE69220399D1 (de) 1997-07-24
DE69220399T2 (de) 1998-01-02

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