KR960026279A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

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Publication number
KR960026279A
KR960026279A KR1019940039107A KR19940039107A KR960026279A KR 960026279 A KR960026279 A KR 960026279A KR 1019940039107 A KR1019940039107 A KR 1019940039107A KR 19940039107 A KR19940039107 A KR 19940039107A KR 960026279 A KR960026279 A KR 960026279A
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KR
South Korea
Prior art keywords
tungsten
semiconductor device
etching
gas
manufacturing
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KR1019940039107A
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English (en)
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KR0148293B1 (ko
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019940039107A priority Critical patent/KR0148293B1/ko
Publication of KR960026279A publication Critical patent/KR960026279A/ko
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Publication of KR0148293B1 publication Critical patent/KR0148293B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 금속 배선 공정시 배선의 효과를 최대화하기 위하여 제조되는 텅스텐 플러그(W-plug)를 증착 후, 식각하는 공정에서, SF6와 O2 가스를 사용하여, 등방성 식각 효과를 최대화하면서, TiOxFy계의 폴리머를 발생하지 않도록 블랭키트 텅스텐 에치백(etch back)을 행하는 반도체 소자의 제조 방법에 관한 것이다. 종래에는, 블랭키트 텅스텐 -에치백시, 과도식각이 심하면, 콘택홀 내부의 텅스텐 손실이 심하고 또한 식각이 불충분하게 이루어지면 SF6 + Ar 가스에의하여 비등방성 식각을 하므로, 제거된 하부층의 표면에 텅스텐 잔류물이 남는 문제점이 있었다. 따라서, 본 발명은 반도체 소자의 다층 배선 연결을 위한 텅스텐 - 플러그를 형성하는 반도체 소자의 제조 방법으로써, 소정의 절연막에 콘택홀을 형성하고, 장벽(barrier) 금속막 및 텅스텐막을 적층한 다음에, SF6와 O2 가스를 사용하여, 블랭키트 텅스텐 에치백을 2단계 식각법으로 실시하는 것을 특징으로 한다.

Description

반도체 소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 (a) 및 (b)는 SF6+ Ar 가스에 의한 식각 후, 매질의 조성물 분포 상태를 나타낸 그래프.
제5도 (a) 및 (b)는 SF6+ O2 가스에 의한 식각 후, 매질의 조성물 분포 상태를 나타낸 그래프.

Claims (3)

  1. 반도체 소자의 다층배선 연결을 위한 텅스텐-플로그를 형성하는 반도체 소자의 제조 방법에 있어서, 소정의 절연막에 콘택홀을 형성하고, 장벽(barrier) 금속막 및 텅스텐막을 적층한 다음에, SF6+와 O2가스를 사용하여 종말점에치백을 실시하는 단계; 과도 에치백을 실시하는 단계로 구성되는 것을 특징으로 하는 반도체 소자의 제조 방법.
  2. 제1항에 있어서, 상기 종말점 에치백 공정은 SF6+ 20% 이하의 O2가스에 의하여 진행됨을 특징으로하는 반도체 소자의 제조 방법.
  3. 제1항에 있어서, 과도 에치백 공정은 SF6+ 20 ∼ 40%이하의 O2가스에 의하여 진행됨을 특징으로 하는 반도체 소자의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940039107A 1994-12-30 1994-12-30 반도체 소자의 제조방법 KR0148293B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039107A KR0148293B1 (ko) 1994-12-30 1994-12-30 반도체 소자의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039107A KR0148293B1 (ko) 1994-12-30 1994-12-30 반도체 소자의 제조방법

Publications (2)

Publication Number Publication Date
KR960026279A true KR960026279A (ko) 1996-07-22
KR0148293B1 KR0148293B1 (ko) 1998-12-01

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KR1019940039107A KR0148293B1 (ko) 1994-12-30 1994-12-30 반도체 소자의 제조방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100307161B1 (ko) * 1999-05-13 2001-09-26 황인길 반도체 소자의 금속 배선층 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100307161B1 (ko) * 1999-05-13 2001-09-26 황인길 반도체 소자의 금속 배선층 형성 방법

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Publication number Publication date
KR0148293B1 (ko) 1998-12-01

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