KR960026219A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR960026219A
KR960026219A KR1019940039109A KR19940039109A KR960026219A KR 960026219 A KR960026219 A KR 960026219A KR 1019940039109 A KR1019940039109 A KR 1019940039109A KR 19940039109 A KR19940039109 A KR 19940039109A KR 960026219 A KR960026219 A KR 960026219A
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KR
South Korea
Prior art keywords
tungsten
deposition
manufacturing
semiconductor device
deposition temperature
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KR1019940039109A
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English (en)
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KR100321141B1 (ko
Inventor
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019940039109A priority Critical patent/KR100321141B1/ko
Publication of KR960026219A publication Critical patent/KR960026219A/ko
Application granted granted Critical
Publication of KR100321141B1 publication Critical patent/KR100321141B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 보다 구체적으로는 콘택홀에 텅스텐 플러그를 형성하는 공정에 있어서, 텅스텐 증착온도를 다단계로 변화시켜 증착을 실시하는 반도체 장치의 제조방법에 관한 것이다. 종래에는 텅스텐을 일정한 증착온도에서 증착함으로 콘택홀 부위의 텅스텐 막의 표면상에 발생하는 요홈의 발생을 전혀 조절할 수 없어 이후의 금속배선형성시 상기 요홈부위에서 금속배선이 얇아짐으로 인하여 금소배선의 단선불량이 일어나는 문제점이 있었다. 본 발명은 텅스텐 플러그를 형성을 위한 텅스텐 막의 증착공정에서, 텅스텐의 증착온도를 다단계로 변화시켜 증착을 실시하여, 텅스텐 플러그의 형성시 텅스텐 플러그의 상부표면상에 요홈의 크기를 최소화하는 것을 특징으로 한다. 따라서, 금속 배선막의 피복력 악화등 금속배선에 관련된 신뢰성을 향상시킬 수 있다.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(가) 내지 (다)는 본 발명의 일 실시예의 제조방법을 설명하기 위한 각 제조공정에 있어서의 반도체장치의 요부 단면도.

Claims (4)

  1. 도전체상에 형성된 절연체에 콘택홀을 형성하고, 콘택홀에 텅스텐 플러그를 형성하는 반도체 장치의 제조방법에 있어서, 상기 텅스텐 플러그를 형성을 위한 텅스텐 막의 증착공정에서, 텅스텐의 증착온도를 다단계로 변화시켜 증착을 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 상기 증착온도는 1차 증착온도가 430~460℃이고, 2차 증착온도가 400~430℃이며, 3차 증착온도가 370~400℃인 것을 특징으로 하는 반도체 소자의 제조방법.
  3. 제1항에 있어서, 상기 다단계 증착 공정에 의하여 형성된 텅스텐 막을 식각하는 공정에서 SF와 O2가스에 의한 반응성 이온 식각시의 지연현상을 이용하여 텅스텐 플러그의 요홈부위 발생을 하는 것을 특징으로 하는 반도체 소자의 제조방법.
  4. 제1항 또는 제2항에 있어서, 상기 콘택홀 형성 후, 텅스텐 막 형성전에 장벽 금속을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940039109A 1994-12-30 1994-12-30 반도체장치의제조방법 KR100321141B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039109A KR100321141B1 (ko) 1994-12-30 1994-12-30 반도체장치의제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039109A KR100321141B1 (ko) 1994-12-30 1994-12-30 반도체장치의제조방법

Publications (2)

Publication Number Publication Date
KR960026219A true KR960026219A (ko) 1996-07-22
KR100321141B1 KR100321141B1 (ko) 2002-05-13

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010003207A (ko) * 1999-06-22 2001-01-15 김영환 반도체 소자의 금속배선 형성방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102401177B1 (ko) 2017-08-31 2022-05-24 삼성전자주식회사 반도체 장치

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04142061A (ja) * 1990-10-02 1992-05-15 Sony Corp タングステンプラグの形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010003207A (ko) * 1999-06-22 2001-01-15 김영환 반도체 소자의 금속배선 형성방법

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