KR950033877A - 피씨아이 로컬 버스상의 통합 에스씨에스아이 및 이더넷 제어기 - Google Patents

피씨아이 로컬 버스상의 통합 에스씨에스아이 및 이더넷 제어기 Download PDF

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Publication number
KR950033877A
KR950033877A KR1019950000927A KR19950000927A KR950033877A KR 950033877 A KR950033877 A KR 950033877A KR 1019950000927 A KR1019950000927 A KR 1019950000927A KR 19950000927 A KR19950000927 A KR 19950000927A KR 950033877 A KR950033877 A KR 950033877A
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South Korea
Prior art keywords
noise
digital
output buffers
scsi
circuit portion
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KR1019950000927A
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English (en)
Inventor
우 치-시웅
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레이 프리쯔
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 레이 프리쯔, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 레이 프리쯔
Publication of KR950033877A publication Critical patent/KR950033877A/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Small-Scale Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PCI로컬 버스에서 사용되는 통합 이더넷-SCSI제어기를 형성하는 SCSI 및 이더넷 어댑터 보드의 구성요소를 단일 칩으로 집적시키는 것이다. 집적은 잡음의 감소에 의해 가능해진다. 전류를 일정하게 스위칭하는 대 PCI 및 SCSI 출력버퍼를 지원하기 위해서 부가적인 Vss핀을 제공함으로써 그라운드 바운스를 감소시킴에 의해 잡음은 처음 감소되어진다. 대 PCI 및 SCSI 출력버퍼를 지원하는 Vss핀은 개별적인 라인에 의해 핀에 접속되는 바와 같은 핀의 로컬 영역에 위치되는 제한된 수의 출력버퍼를 지원한다. 잡음은 디지털 출력버퍼상에 회로를 제공함에 의해 부가적으로 감소되어짐으로서 출력버퍼의 스위칭동안 시간에 대한 전류의 변화(di/dt)를 제한하게 된다. 잡음은 전류 밀도가 아날로그회로로부터 반대방향에서 증가하도록 디지탈 제어회로를 배치시킴에 의해 또한 감소되어진다. 최종적으로, 조합된 이더넷-SCSI제어기의 아날로기부, 디지탈부 및 디지탈 I/O 버퍼부에 있어서 파워 서플라이사이의 양방향 실리콘 제어 정류기를 포함함으로써 잡음이 감소되어진다.

Description

피씨아이 로컬 버스상의 통합 에스씨에스아이 및 이더넷 제어기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 조합된 이더넷-SCSI제어기를 구성요소의 블럭도, 제9도는 이더넷 아날로그 및 디지털 영역에서 소오스 파워 라인의 구조 및 디지탈 I/O버퍼회로로부터의 레이아웃의 도시도.

Claims (7)

  1. 단일 집적회로, 칩으로 집적된 SCSI제어기 및 이더넷 제어기를 포함하는 것을 특징으로 하는 장치.
  2. 제1항에 있어서, 최대 다섯개의 어드레스 혹은 데이타 출력버퍼가 단일 VSS3B핀으로 접속되도록 제공되는 다수의 VSS3B핀 접속을 포함하는 것을 특징으로 하는 장치.
  3. 제2항에 있어서, 단지 하나의 입력버퍼만을 다수의 VSS3B핀에서 하나의 VSS3B핀으로 각각 접속시키는 다수의 접속 라인을 포함하는 것을 특징으로 하는 장치.
  4. 제1항에 있어서, 출력버퍼는 세 개의 풀업 트랜지스터를 포함하고 , 각각의 풀업 트랜지스터는 출력버퍼의 출력 전류에 있어서의 증가를 제한하도록 시간 지연에 의해 분리되어 인에이블되는 것을 특징으로 하는 장치.
  5. 제1항에 있어서, 아날로그 회로부와, 디지탈 회로부를 포함하고, 여기서 디지탈 제어회로부에서의 전류밀도가 아날로그회로부로부터 반대방향으로 증가하는 것을 특징으로 하는 장치.
  6. 제1항에 있어서, 제1파워 서플라이를 갖는 아날로그회로부와, 제2파워 서플라이를 갖는 디지탈 제어회로부와, 제3파워 서플라이를 갖는 디지탈 I/O버퍼부와, 제1, 제2 및 제3파워 서플라이를 분리시키는 다수의 실리콘 제어 정류기를 포함하는 것을 특징으로 하는 장치.
  7. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950000927A 1994-01-24 1995-01-20 피씨아이 로컬 버스상의 통합 에스씨에스아이 및 이더넷 제어기 KR950033877A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/186,050 US6295572B1 (en) 1994-01-24 1994-01-24 Integrated SCSI and ethernet controller on a PCI local bus
US8/186,050 1994-01-24

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Publication Number Publication Date
KR950033877A true KR950033877A (ko) 1995-12-26

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US (1) US6295572B1 (ko)
EP (1) EP0664513B1 (ko)
JP (1) JP3976803B2 (ko)
KR (1) KR950033877A (ko)
AT (1) ATE216789T1 (ko)
DE (1) DE69526466T2 (ko)

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Publication number Publication date
EP0664513B1 (en) 2002-04-24
US6295572B1 (en) 2001-09-25
DE69526466T2 (de) 2002-12-05
EP0664513A1 (en) 1995-07-26
JPH07271703A (ja) 1995-10-20
ATE216789T1 (de) 2002-05-15
DE69526466D1 (de) 2002-05-29
JP3976803B2 (ja) 2007-09-19

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