DE69526466T2 - Integrierter SCSI/ und Ethernetsteuerungsschaltkreis für PCI-Lokalbus - Google Patents

Integrierter SCSI/ und Ethernetsteuerungsschaltkreis für PCI-Lokalbus

Info

Publication number
DE69526466T2
DE69526466T2 DE69526466T DE69526466T DE69526466T2 DE 69526466 T2 DE69526466 T2 DE 69526466T2 DE 69526466 T DE69526466 T DE 69526466T DE 69526466 T DE69526466 T DE 69526466T DE 69526466 T2 DE69526466 T2 DE 69526466T2
Authority
DE
Germany
Prior art keywords
noise
scsi
output buffers
digital
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69526466T
Other languages
English (en)
Other versions
DE69526466D1 (de
Inventor
Chih-Siung Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69526466D1 publication Critical patent/DE69526466D1/de
Application granted granted Critical
Publication of DE69526466T2 publication Critical patent/DE69526466T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Small-Scale Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE69526466T 1994-01-24 1995-01-17 Integrierter SCSI/ und Ethernetsteuerungsschaltkreis für PCI-Lokalbus Expired - Lifetime DE69526466T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/186,050 US6295572B1 (en) 1994-01-24 1994-01-24 Integrated SCSI and ethernet controller on a PCI local bus

Publications (2)

Publication Number Publication Date
DE69526466D1 DE69526466D1 (de) 2002-05-29
DE69526466T2 true DE69526466T2 (de) 2002-12-05

Family

ID=22683460

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526466T Expired - Lifetime DE69526466T2 (de) 1994-01-24 1995-01-17 Integrierter SCSI/ und Ethernetsteuerungsschaltkreis für PCI-Lokalbus

Country Status (6)

Country Link
US (1) US6295572B1 (de)
EP (1) EP0664513B1 (de)
JP (1) JP3976803B2 (de)
KR (1) KR950033877A (de)
AT (1) ATE216789T1 (de)
DE (1) DE69526466T2 (de)

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US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
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US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
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US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
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US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
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US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US7379316B2 (en) 2005-09-02 2008-05-27 Metaram, Inc. Methods and apparatus of stacking DRAMs
JP4946000B2 (ja) * 2005-10-24 2012-06-06 セイコーエプソン株式会社 集積回路装置及び電子機器
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Also Published As

Publication number Publication date
JP3976803B2 (ja) 2007-09-19
US6295572B1 (en) 2001-09-25
JPH07271703A (ja) 1995-10-20
KR950033877A (ko) 1995-12-26
DE69526466D1 (de) 2002-05-29
ATE216789T1 (de) 2002-05-15
EP0664513A1 (de) 1995-07-26
EP0664513B1 (de) 2002-04-24

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GARAND CAYMAN, KY