KR950009982A - 박막트랜지스터의 제조방법 - Google Patents

박막트랜지스터의 제조방법 Download PDF

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KR950009982A
KR950009982A KR1019940024166A KR19940024166A KR950009982A KR 950009982 A KR950009982 A KR 950009982A KR 1019940024166 A KR1019940024166 A KR 1019940024166A KR 19940024166 A KR19940024166 A KR 19940024166A KR 950009982 A KR950009982 A KR 950009982A
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gate electrode
semiconductor layer
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시게루 아오모리
아쯔시 요시노우찌
게이지 다루이
다쯔오 모리따
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쯔지 하루오
샤프 가부시끼가이샤
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Abstract

본 발명의 박막트랜지스터의 제조방법은, 절연성기판상에 반도체층과 게이트전극간에 게이트절연막이 개재하도록 반도체층과 게이트전극을 형성하는 공정; 상기 게이트전극, 및 이 게이트전극 형성시에 사용된 레지스트마스크중 적어도 하나를 마스크로 하여, 상기 반도체층의 채널부의 수소이온농도가 1×1019ion/㎤ 내지 1×1020ion/㎤의 범위로 제어되도록 상기 반도체층 표면에 주기율표 제Ⅲ족 원소이온과 수소이온, 또는 주기율표 제Ⅴ족 원소이온과 수소이온중 하나를 가속하여 불순물원소의 주입을 행하여, 소스 및 드레인영역들의 형성과 동시에 채널부의 수소화를 행하는 공정을 포함한다.

Description

박막트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 있어서의 CMOS 구조를 갖는 TFT의 평면도이다.
제2도는 제1도의 A-A′선에 따른 TFT의 단면도이다.
제3도는 제1도에 보인 TFT로 불순물을 주입하기 위해 사용되는 이온 샤워 도핑장치의 개략 단면도이다.
제4도는 LSS이론에 기초하여, 박막내로 주입된 수소이온의 농도분포를 깊이방향으로 도시한 도면이다.
제5a도 내지 제5c도는 제1도에 보인 TFT의 제조공정들을 나타낸 평면도이다.

Claims (12)

  1. 절연기판상에 반도체층과 게이트전극간에 게이트절연막이 개재하도록 반도체층과 게이트전극을 형성하는 공정; 및 상기 게이트전극, 및 이 게이트전극형성시에 사용돈 레지스트마스크중 적어도 하나를 마스크로 하여, 상기 반도체층의 채널부의 수소이온농도가 1×1019ion/㎤ 내지 1×1020ion/㎤의 범위로 제어되도록 상기 반도체층 표면에 주기율표 제Ⅲ족 원소이온과 수소이온, 또는 주기율표 제Ⅴ족 원소이온과 수소이온중 하나를 가속하여 불순물원소의 주입을 행하여, 소스 및 드레인영역들의 형성과 동시에 채널부의 수소화를 행하는 공정을 포함하는 박막트랜지스터의 제조방법.
  2. 제1항에 있어서, 상기 반도체층이 다결정실리콘으로 형성되는 박막트랜지스터의 제조방법.
  3. 제1항에 있어서, 상기 게이트전극이 적어도 알루미늄, 알루미늄을 함유하는 금속, 및 알루미늄과 알루미늄 이외의 금속의 적층체를 포함하는 군으로 부터 선택되는 재료로 형성되는 박막트랜지스터의 제조방법.
  4. 제1항에 있어서, 상기 불순물원소의 주입을 행하는 공정이후의 공정들이 450℃ 이하에서 행해지는 박막트랜지스터의 제조방법.
  5. 절연성 기판상에 반도체층을 형성하는 공정; 상기 반도체층상에 게이트절연막을 형성하는 공정; 상기 게이트절연막상에 게이트전극을 형성하는 공정; 및 상기 게이트전극을 마스크로 하여, 채널부의 수소이온농도가 1×1019ion/㎤ 내지 1×1020ion/㎤의 범위로 제어되도록 상기 반도체층 표면에 주기율표 제Ⅲ족 원소이온과 수소이온, 또는 주기율표 제Ⅴ족 원소이온과 수소이온중 하나를 가속하여 불순물원소의 주입을 행하여, 소스 및 드레인영역들의 형성과 동시에 채널부의 수소화를 행하는 공정을 포함하는 박막트랜지스터의 제조방법.
  6. 제5항에 있어서, 상기 반도체층이 다결정실리콘으로 형성되는 박만트랜지스터의 제조방법.
  7. 제5항에 있어서, 상기 게이트전극이 적어도 알루미늄, 알루미늄을 함유하는 금속, 알루미늄과 알루미늄 이외의 금속의 적층체를 포함하는 군으로 부터 선택되는 재료로 형성되는 박막트랜지스터의 제조방법.
  8. 제5항에 있어서, 상기 불순물원소의 주입을 행하는 공정이후의 공정들이 450℃ 이하에서 행해지는 박막트랜지스터의 제조방법.
  9. 절연성 기판상에 반도체층을 형성하는 공정; 상기 반도체층상에 게이트절연막을 형성하는 공정; 상기 게이트절연막상에 도전성박막을 형성하는 공정; 상기 도전성박막상에 소정 형상의 레지스트패턴을 형성하는 공정; 상기 레지스트패턴을 마스크로 하여 도전성 박막으로 부터 게이트전극과 게이트 전극 배선을 형성하는 공정; 및 상기 레지스트패턴과 게이트전극을 마스크로 하여, 채널부의 수소이온농도가 1×1019ion/㎤ 내지 1×1020ion/㎤의 범위로 제어되도록 상기 반도체층 표면에 주기율표 제Ⅲ족 원소이온과 수소이온, 또는 주기율표 제Ⅴ족 원소이온과 수소이온중 하나를 가속하여 불순물원소의 주입을 행하여, 소스 및 드레인영역들의 형성과 동시에 채널부의 수소화를 행하는 공정을 포함하는 박막트랜지스터의 제조방법.
  10. 제9항에 있어서, 상기 반도체층이 다결정실리콘으로 형성되는 박막트랜지스터의 제조방법.
  11. 제9항에 있어서, 상기 게이트전극이 적어도 알루미늄, 알루미늄을 함유하는 금속, 알루미늄과 알루미늄 이외의 금속의 적층체를 포함하는 군으로 부터 선택되는 재료로 형성되는 박막트랜지스터의 제조방법.
  12. 제9항에 있어서, 상기 불순물원소의 주입을 행하는 공정이후의 공정들이 450℃ 이하에서 행해지는 박막트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940024166A 1993-09-22 1994-09-22 박막트랜지스터의 제조방법 KR0145267B1 (ko)

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JP23661093 1993-09-22
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JP6177076A JPH07142743A (ja) 1993-09-22 1994-07-28 薄膜トランジスタの製造方法
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EP0645803B1 (en) 2001-08-22
DE69428014D1 (de) 2001-09-27
EP0645803A2 (en) 1995-03-29
JPH07142743A (ja) 1995-06-02
DE69428014T2 (de) 2002-04-18
KR0145267B1 (ko) 1998-08-17
US5504020A (en) 1996-04-02
EP0645803A3 (en) 1997-03-05

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