KR950009904A - 입자 크기가 큰 다결정 규소 박막의 제조 방법 - Google Patents

입자 크기가 큰 다결정 규소 박막의 제조 방법 Download PDF

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KR950009904A
KR950009904A KR1019930017870A KR930017870A KR950009904A KR 950009904 A KR950009904 A KR 950009904A KR 1019930017870 A KR1019930017870 A KR 1019930017870A KR 930017870 A KR930017870 A KR 930017870A KR 950009904 A KR950009904 A KR 950009904A
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thin film
silicon thin
polycrystalline silicon
particle size
substrate
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KR1019930017870A
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KR970006723B1 (ko
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임호빈
안병태
문대규
이정노
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천성순
한국과학 기술원
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Priority to KR1019930017870A priority Critical patent/KR970006723B1/ko
Priority to US08/282,643 priority patent/US5470619A/en
Publication of KR950009904A publication Critical patent/KR950009904A/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24Deposition of silicon only

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명에 기판상에 비정질 규소 박막을 증착시킨 후, 이를 특정 압력 하에 저온에서 열처리하여 고상 결정화시키는 것으로 이루어진 입자 크기가 큰 다결정 규소 박막을 제조하는 방법이 기재되어 있다. 본 발명의 방법은 결정 성장 온도를 크게 낮춤으로써 값비싼 석영 대신 값싼 유리 등의 기판을 사용하고, 고가의 Si2H6가스 대신 SiH4가스를 사용함으로써 다결정 규소 박막의 생산 단가를 크게 낮출 수 있을 뿐 만 아니라, 입자 크기가 150μ이상인 다결정 규소 박막을 제공함으로써 다결정 규소 박막의 전자 및 정공의 이동도를 단결정 수준으로 향상시켜 현재 어려움을 겪고 있는 LCD용 TFT나 SRAM용 TFT등의 고성능 SOI소자 개발을 획기적으로 진전시킬 수 있다.

Description

입자 크기가 큰 다결정 규소 박막의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 다결정 규소 박막 제조 방법의 제조 공정을 도시한 흐름도,
제2도는 본 발명의 방법으로 제조된 다결정 규소 박막의 증착 온도에 다른 입자 크기를 나타내는 그래프,
제3도는 종래의 방법으로 제조된 다결정 규소 박막의 증착 온도에 따른 입자 크기를 나타내는 그래프,
제4a도는 본 발명의 방법으로 제조된 다결정 규소 박막(두께 약 1,000Å)의 사진,
제4b도는 종래의 방법으로 제조된 다결정 규소 박막(두께 약 1,000Å)의 사진.

Claims (6)

  1. 기판 상에 비정질 규소 박막을 PECVD, LPCVD 등의 공지 방법으로 증착시킨 후, 10-9내지 103토르의 압력 범위 하에 300내지 600℃의 온도 범위에서 열처리함으로써 고상 결정화시키는 것을 특징으로 하는 입자 크기가 큰 다결정 규소박막의 제조 방법.
  2. 제1항에 있어서, 상기 기판이 유리판, 석영판, Si 웨이퍼, 또는 비정질(SiO2, 질화규소, 실리콘 옥시-니트라이드, 산화 탄달)이 입혀진 유리판, 석영판 또는 Si 웨이퍼인 것인 방법.
  3. 제1항에 있어서, 상기 규소 박막의 증착시에 SiH4, Si2H6또는 이들 기체를 Ar, He, H2또는 N2가스로 희석시킨 것을 원료 기체로 사용하는 것인 방법.
  4. 제1항에 있어서, 증착된 규소 박막이 10-2토르의 압력에서 N2또는 Ar기체분위기 하에 500℃에서 열처리하여 고상 결정화되는 것인 방법.
  5. 제1항 기재의 방법에 따라 제조한, 입자 크기가 150㎛이상인 다결정 규소 박막.
  6. 제5항에 있어서, 상기 다결정 규소 박막이 SOI, TFT, 태양 전지 등의 제조에 사용되는 것인 다결정 규소 박막.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930017870A 1993-09-07 1993-09-07 입자 크기가 큰 다결정 규소 박막의 제조방법 KR970006723B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019930017870A KR970006723B1 (ko) 1993-09-07 1993-09-07 입자 크기가 큰 다결정 규소 박막의 제조방법
US08/282,643 US5470619A (en) 1993-09-07 1994-07-29 Method of the production of polycrystalline silicon thin films

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KR1019930017870A KR970006723B1 (ko) 1993-09-07 1993-09-07 입자 크기가 큰 다결정 규소 박막의 제조방법

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KR950009904A true KR950009904A (ko) 1995-04-26
KR970006723B1 KR970006723B1 (ko) 1997-04-29

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2900229B2 (ja) 1994-12-27 1999-06-02 株式会社半導体エネルギー研究所 半導体装置およびその作製方法および電気光学装置
US5834327A (en) 1995-03-18 1998-11-10 Semiconductor Energy Laboratory Co., Ltd. Method for producing display device
JP3174486B2 (ja) * 1995-09-08 2001-06-11 シャープ株式会社 太陽電池およびその製造方法
AU2452697A (en) * 1996-04-10 1997-10-29 Penn State Research Foundation, The Modifying solid crystallization kinetics for a-si films
US5834068A (en) * 1996-07-12 1998-11-10 Applied Materials, Inc. Wafer surface temperature control for deposition of thin films
US5773329A (en) * 1996-07-24 1998-06-30 International Business Machines Corporation Polysilicon grown by pulsed rapid thermal annealing
US5707895A (en) * 1996-10-21 1998-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Thin film transistor performance enhancement by water plasma treatment
US5908307A (en) * 1997-01-31 1999-06-01 Ultratech Stepper, Inc. Fabrication method for reduced-dimension FET devices
JP3027968B2 (ja) * 1998-01-29 2000-04-04 日新電機株式会社 成膜装置
US6294219B1 (en) * 1998-03-03 2001-09-25 Applied Komatsu Technology, Inc. Method of annealing large area glass substrates
US6197669B1 (en) * 1999-04-15 2001-03-06 Taiwan Semicondcutor Manufacturing Company Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process
DE19935046C2 (de) 1999-07-26 2001-07-12 Schott Glas Plasma-CVD-Verfahren und Vorrichtung zur Herstellung einer mikrokristallinen Si:H-Schicht auf einem Substrat sowie deren Verwendung
JP3806751B2 (ja) * 2000-05-23 2006-08-09 独立行政法人科学技術振興機構 量子サイズ効果型微小電子銃の製造方法
US6726955B1 (en) * 2000-06-27 2004-04-27 Applied Materials, Inc. Method of controlling the crystal structure of polycrystalline silicon
KR100578105B1 (ko) * 2003-12-30 2006-05-10 한국과학기술원 알루미늄 할로겐 화합물과 이종 금속 화합물의 혼합분위기를 이용한 다결정 규소박막의 제조방법
FR2950082B1 (fr) * 2009-09-14 2011-10-14 Commissariat Energie Atomique Procede de recristallisation d'une couche
CN111834207B (zh) * 2019-04-22 2023-06-16 上海新微技术研发中心有限公司 一种沉积多晶硅薄膜的方法
CN113913791B (zh) * 2021-09-29 2024-03-01 湖南红太阳光电科技有限公司 一种多层非晶硅薄膜的制备方法及太阳能电池

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4406709A (en) * 1981-06-24 1983-09-27 Bell Telephone Laboratories, Incorporated Method of increasing the grain size of polycrystalline materials by directed energy-beams
EP0307109A1 (en) * 1987-08-24 1989-03-15 Canon Kabushiki Kaisha Method for forming semiconductor crystal and semiconductor crystal article obtained by said method
WO1990003453A1 (en) * 1988-09-28 1990-04-05 Oki Electric Industry Co., Ltd. Process for forming superconducting thin film
JPH03256333A (ja) * 1990-03-07 1991-11-15 Hitachi Ltd 半導体装置の製造方法
US5318919A (en) * 1990-07-31 1994-06-07 Sanyo Electric Co., Ltd. Manufacturing method of thin film transistor
JP2856533B2 (ja) * 1990-10-05 1999-02-10 株式会社東芝 多結晶シリコン薄膜の製造方法
JPH05343316A (ja) * 1991-09-30 1993-12-24 Nec Corp 半導体装置の製造方法

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