KR960026967A - 다결정 박막 트랜지스터 및 그 제조방법 - Google Patents

다결정 박막 트랜지스터 및 그 제조방법 Download PDF

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KR960026967A
KR960026967A KR1019940036339A KR19940036339A KR960026967A KR 960026967 A KR960026967 A KR 960026967A KR 1019940036339 A KR1019940036339 A KR 1019940036339A KR 19940036339 A KR19940036339 A KR 19940036339A KR 960026967 A KR960026967 A KR 960026967A
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South Korea
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thin film
polycrystalline
film transistor
polycrystalline silicon
germanium
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KR1019940036339A
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KR0155304B1 (ko
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송윤호
남기수
김보우
백종태
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양승택
재단법인 한국전자통신연구소
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 전기적 특성을 향상시킨 새로운 구조의 박막 트랜지스터 및 이를 구현하기 위한 제조 방법에 관한 것으로서, 결정 실리콘(20)과 다결정 실리콘 저마늄(21)은 화학기상증착법을 이용하여 비정실 실리콘 박막(201), 비정실 실리콘 저마늄 박막(211), 비정실 실리콘 박막(202)을 순차적으로 증착한 후 600℃ 이하의 온도에서 전기로 열처리에 의한 고상결정화나, 600℃ 이상의 온도에서 급속 열처리로 결정핵을 생성한 후 600℃ 이하의 전기로에서 결정립을 성장시키는 공정에 의해 제조된다.

Description

다결정 박막 트랜지스터 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 다결정 박막 트랜지스터 구조를 나타내는 단면도, 제3도는 본 발명에 의한 다결정 박막 트랜지스터의 제조공정을 설명하기 위한 단면도.

Claims (5)

  1. 다결정 박막 트랜지스터의 있어서, 투명 절연기판 또는 절연막이 형성되어 있는 실리콘 웨이퍼 10상에 진성 다경정 실리콘 박막(20)사이에 진성 다결정 실리콘 저마늄(21)이 삽입된 형태의 3층 구조로 된 활성층과, 상기 다결정 실리콘(20)과 실리콘 저마늄(21)위에서 형성된 게이트 산화막(30)과, 상기 게이트 산화막(30)위에 게이트 전극(40)을 형성한 후 도펀트 불순물을 이온 주입하여 만든소오스 및 드레인(50)과, 상기 게이트 산화막(30)과 게이트 전극(40)위에 형성된 보호산화막(60)과, 상기 보호산화막(60)를 패터닝하여 전극 접촉구멍을 형성한 후 상기 소오스 및 드레인(50)과 전기적으로 연결된 금속 전극 70을 포함하는 다결정 박막 트랜지스터.
  2. 제1항에 있어서, 상기 진성 다결정 실리콘(20)의 두께는 100∼1,000A인 것을 특징으로 하는 는 다결정 박막 트랜지스터.
  3. 제1항에 있어서, 상기 진성 다결정 실리콘(20)의 두께는 50∼500A인 것을 특징으로 하는 는 다결정 박막 트랜지스터.
  4. 제1항에 있어서, 상기 진성 다결정 실리콘저마늄(21)의 저마늄 몰비는 0.05∼0.5인 것을 특징으로 하는 는 다결정 박막 트랜지스터.
  5. 상기 다결정 실리콘(20)과 다결정 실리콘저마늄(21)은 화학기상증착법을 이용하여 비정질 실리콘 박막(201), 비정질 실리콘 저마늄 박막(211), 비정질 실리콘 박막(202)을 순차적으로 증착한 후 600°C이하의 온도에서 전기로 열처리에 의한 고상결정화나, 600°C이상의 온도에서 급속 열처리로 결정핵을 생성한후 600°C이하의 전기로에서 결정립을 성장시키는 고정을 포함하는 것을 특징으로 하는 다결정 박막 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940036339A 1994-12-23 1994-12-23 다결정 박막 트랜지스터 및 그 제조방법 KR0155304B1 (ko)

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KR1019940036339A KR0155304B1 (ko) 1994-12-23 1994-12-23 다결정 박막 트랜지스터 및 그 제조방법

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KR1019940036339A KR0155304B1 (ko) 1994-12-23 1994-12-23 다결정 박막 트랜지스터 및 그 제조방법

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359022B1 (ko) * 2000-12-20 2002-10-31 엘지.필립스 엘시디 주식회사 폴리실리콘형 박막트랜지스터 제조 방법
KR100357173B1 (ko) * 1996-07-31 2003-01-24 주식회사 하이닉스반도체 박막 트랜지스터의 제조 방법
KR100704331B1 (ko) * 2001-01-26 2007-04-09 가부시키가이샤 히타치세이사쿠쇼 박막 트랜지스터 장치

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100357173B1 (ko) * 1996-07-31 2003-01-24 주식회사 하이닉스반도체 박막 트랜지스터의 제조 방법
KR100359022B1 (ko) * 2000-12-20 2002-10-31 엘지.필립스 엘시디 주식회사 폴리실리콘형 박막트랜지스터 제조 방법
KR100704331B1 (ko) * 2001-01-26 2007-04-09 가부시키가이샤 히타치세이사쿠쇼 박막 트랜지스터 장치

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