KR940007975A - 박막 트랜지스터의 채널폴리 제조방법 - Google Patents

박막 트랜지스터의 채널폴리 제조방법 Download PDF

Info

Publication number
KR940007975A
KR940007975A KR1019920017795A KR920017795A KR940007975A KR 940007975 A KR940007975 A KR 940007975A KR 1019920017795 A KR1019920017795 A KR 1019920017795A KR 920017795 A KR920017795 A KR 920017795A KR 940007975 A KR940007975 A KR 940007975A
Authority
KR
South Korea
Prior art keywords
thin film
grain size
silicon thin
temperature
film transistor
Prior art date
Application number
KR1019920017795A
Other languages
English (en)
Other versions
KR950010859B1 (ko
Inventor
우상호
전하응
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920017795A priority Critical patent/KR950010859B1/ko
Priority to US08/127,968 priority patent/US5429961A/en
Priority to JP5242998A priority patent/JPH0817239B2/ja
Publication of KR940007975A publication Critical patent/KR940007975A/ko
Application granted granted Critical
Publication of KR950010859B1 publication Critical patent/KR950010859B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명은 고집적반도체의 SRAM용 박막트랜지스터의 채널폴리 제조방법에 관한 것으로, 다결정 실리콘박막의 그레인 사이즈를 크게 하기 위하여, 소정의 물질층 상부에 510~550℃의 온도에서 SiH4개스를 이용하여 비정질 실리콘박막을 증착하되 박막의 두께 균일성을 유지할 수 있는 범위의 압력에서 증착하는 단계와, 상기 증착된 비정질 실리콘박막을 동일 튜브내에서 압력을 10-3Torr로 낮추고, 온도는 600~650℃로 상승시키고, 4~10시간동안 어닐처리하여 그레인 사이즈가 극대화된 다결정시릴콘박막을 형성하는 단계로 이루어지는 기술이다.

Description

박막 트랜지스터의 채널폴리 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 의해 박막 트랜지스터 (TFT)의 채널폴리 제조단계를 도시한 단면도.

Claims (2)

  1. 박막 트랜지스터의 채널폴리 제조방법에 있어서, 다결정 실리콘박막의 그레인 사이즈를 크게 하기 위하여, 소정의 물질층 상부에 510~550℃의 온도에서 SiH4개스를 이용하여 비정질 실리콘박막을 증착하되 박막의 두께 균일성을 유지할 수 있는 범위의 압력에서 증착하는 단계와, 상기 증착된 비정질 실리콘박막을 동일 튜브내에서 압력을 10-3Torr로 낮추고, 온도는 600~650℃로 상승시키고, 4~10시간동안 어닐처리하여 그레인 사이즈가 극대화된 다결정실리콘박막을 형성하는 단계로 이루어지는 것을 특징으로 하는 박막 트랜지스터의 채널폴리 제조방법.
  2. 제1항에 있어서, 상기 비정질 실리콘박막을 증착하는 압착은 1Torr정도인 것을 특징으로 하는 박막 트랜지스터의 채널폴리 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920017795A 1992-09-29 1992-09-29 박막 트랜지스터의 채널폴리 제조방법 KR950010859B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920017795A KR950010859B1 (ko) 1992-09-29 1992-09-29 박막 트랜지스터의 채널폴리 제조방법
US08/127,968 US5429961A (en) 1992-09-29 1993-09-28 Method for manufacturing a thin film transistor
JP5242998A JPH0817239B2 (ja) 1992-09-29 1993-09-29 薄膜トランジスタの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920017795A KR950010859B1 (ko) 1992-09-29 1992-09-29 박막 트랜지스터의 채널폴리 제조방법

Publications (2)

Publication Number Publication Date
KR940007975A true KR940007975A (ko) 1994-04-28
KR950010859B1 KR950010859B1 (ko) 1995-09-25

Family

ID=19340292

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920017795A KR950010859B1 (ko) 1992-09-29 1992-09-29 박막 트랜지스터의 채널폴리 제조방법

Country Status (3)

Country Link
US (1) US5429961A (ko)
JP (1) JPH0817239B2 (ko)
KR (1) KR950010859B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950082A (en) * 1996-09-30 1999-09-07 Advanced Micro Devices, Inc. Transistor formation for multilevel transistors
US6150695A (en) * 1996-10-30 2000-11-21 Advanced Micro Devices, Inc. Multilevel transistor formation employing a local substrate formed within a shallow trench
US7547939B2 (en) * 2005-11-23 2009-06-16 Sensor Electronic Technology, Inc. Semiconductor device and circuit having multiple voltage controlled capacitors

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358326A (en) * 1980-11-03 1982-11-09 International Business Machines Corporation Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing
US4597160A (en) * 1985-08-09 1986-07-01 Rca Corporation Method of fabricating a polysilicon transistor with a high carrier mobility
JPS6310573A (ja) * 1986-07-02 1988-01-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4897360A (en) * 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
JP2880175B2 (ja) * 1988-11-30 1999-04-05 株式会社日立製作所 レーザアニール方法及び薄膜半導体装置
US5180690A (en) * 1988-12-14 1993-01-19 Energy Conversion Devices, Inc. Method of forming a layer of doped crystalline semiconductor alloy material
US5147826A (en) * 1990-08-06 1992-09-15 The Pennsylvania Research Corporation Low temperature crystallization and pattering of amorphous silicon films
JP2987987B2 (ja) * 1991-04-22 1999-12-06 松下電器産業株式会社 結晶半導体薄膜の形成方法並びに薄膜トランジスタの製造方法
JPH05343316A (ja) * 1991-09-30 1993-12-24 Nec Corp 半導体装置の製造方法
US5266504A (en) * 1992-03-26 1993-11-30 International Business Machines Corporation Low temperature emitter process for high performance bipolar devices

Also Published As

Publication number Publication date
US5429961A (en) 1995-07-04
JPH06204252A (ja) 1994-07-22
KR950010859B1 (ko) 1995-09-25
JPH0817239B2 (ja) 1996-02-21

Similar Documents

Publication Publication Date Title
KR930006821A (ko) 감소된 저항률을 갖는 개량된 다결정 실리콘막을 포함하는 반도체 디바이스 제조방법
KR930703707A (ko) 폴리실리콘 박막 트랜지스터
KR950009904A (ko) 입자 크기가 큰 다결정 규소 박막의 제조 방법
KR940007975A (ko) 박막 트랜지스터의 채널폴리 제조방법
JPS59115564A (ja) 薄膜トランジスタの製造方法
KR950021615A (ko) 반도체 소자의 캐패시터 유전체막 형성방법
JPH0661489A (ja) 薄膜トランジスタの製造方法
KR950001900A (ko) 비정질 실리콘 및 다결정 실리콘을 이용한 새로운 전극구조의 형성방법
KR970003426A (ko) 반도체 장치의 제조 방법
KR970054386A (ko) 반도체 장치의 제조방법
KR930009547B1 (ko) SiNx/a-Si 계면 형성 방법
US6300185B1 (en) Polyacrystalline silicon film formation method
KR960018736A (ko) 액정표시장치용 박막 트랜지스터의 제조방법
KR940022752A (ko) 박막 트랜지스터의 채널 폴리 제조방법
KR970054255A (ko) 박막 트랜지스터의 채널 폴리실리콘막 형성 방법
KR960026438A (ko) 박막 트랜지스터 제조방법
KR0179139B1 (ko) 다결정실리콘층 형성방법
KR950007147A (ko) 박막 트랜지스터의 제조방법
KR930001488A (ko) Mos 장치 및 그 제조방법
KR970052894A (ko) 그레인 크기가 증대된 폴리실리콘층 제조방법
KR970003470A (ko) 실리콘 전극의 제조 방법
KR950029380A (ko) 플라즈마 화학기상증착법을 이용한 다결정실리콘막 증착방법
JPH01169932A (ja) 半導体装置の製造方法
KR960019594A (ko) 게이트전극 제조방법
KR910001892A (ko) 포스퍼러스 도우프드 산화물 플로우 공정방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee