KR950004452A - 반도체 집적회로장치 - Google Patents

반도체 집적회로장치 Download PDF

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Publication number
KR950004452A
KR950004452A KR1019940016270A KR19940016270A KR950004452A KR 950004452 A KR950004452 A KR 950004452A KR 1019940016270 A KR1019940016270 A KR 1019940016270A KR 19940016270 A KR19940016270 A KR 19940016270A KR 950004452 A KR950004452 A KR 950004452A
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KR
South Korea
Prior art keywords
well
input terminal
type
buried layer
grounded
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KR1019940016270A
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English (en)
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KR0139873B1 (ko
Inventor
시게토 미즈카미
Original Assignee
사토 후미오
가부시키가이샤 도시바
오카모토 세이시
도시바 마이크로일렉트로닉스 가부시키가이샤
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Application filed by 사토 후미오, 가부시키가이샤 도시바, 오카모토 세이시, 도시바 마이크로일렉트로닉스 가부시키가이샤 filed Critical 사토 후미오
Publication of KR950004452A publication Critical patent/KR950004452A/ko
Application granted granted Critical
Publication of KR0139873B1 publication Critical patent/KR0139873B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Protection Of Static Devices (AREA)

Abstract

본 발명은, 입력보호특성이 높은 보호회로를 구비한 반도체 집적회로장치를 제공하기 위한 것이다.
본 발명은, p형 반도체기판의 표면에 형성된 n형 매립층(12)과, 매립층(12) 위에 형성된 에피택셜층, 이 에피택셜층내에 형성된 p형 웰(16), 에피택셜층내에 형성되는 웰(16)과 전기적으로 분리된 p형 웰(18) 및, 웰(16)에 있어서 일단이 접지 되면서 타단이 입력단자(36)에 접속됨과 더불어 게이트가 입력단자(36)에 접속된 MOS형 트랜지스터(102), 및, 웰(18)내에 있어서 접지된 p형 불순물(26)을 구비하고, 입력단자(36)에 서지전압이 인가될 때 웰(18)내의 불순물영역(27)과, 매립층(12), 웰(16)내의 드레인영역(25) 및, 입력단자(36)와의 사이에 전류가 흐르는 경로(Q1,R2,Q2)가 성립한다.

Description

반도체 집적회로장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 반도체 집적회로장치의 소자구성을 나타낸 종단면도

Claims (1)

1도전형의 반도체기판(11) 표면부분에 형성된 역도전형의 매리층(12)과, 이 매립층(12) 위에 형성된 반도체층, 이 반도체층내에 형성된 1도전형의 제1웰(16), 상기 반도체층내에 형성되면서 상기 제1웰과는 전기적으로 분리된 1도전형의 제2웰(18), 상기 제1웰(16)내에 있어서 일단이 접속되고, 타단이 외부로부터 신호가 입력되는 입력단자(101)에 접속되며, 게이트가 접지된 역도전형의 MOS형 트랜지스터(102) 및, 상기 제2웰내에 있어서 접지된 역도전형의 불순물영역(27)을 구비하고, 상기 입력단자에 서지전압이 인가되었을 때 상기 제2웰내의 상기 불순물영역과 상기 매립층 및, 상기 제1웰내의 상기 타단과 상기 입력단자와의 사이에 전류가 흐르는 경로가 성립하는 것을 특징으로 하는 반도체 집접회로 장치.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940016270A 1993-07-07 1994-07-07 반도체 집적회로장치 KR0139873B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-168053 1993-07-07
JP16805393A JP3246807B2 (ja) 1993-07-07 1993-07-07 半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR950004452A true KR950004452A (ko) 1995-02-18
KR0139873B1 KR0139873B1 (ko) 1998-08-17

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940016270A KR0139873B1 (ko) 1993-07-07 1994-07-07 반도체 집적회로장치

Country Status (3)

Country Link
US (1) US5581103A (ko)
JP (1) JP3246807B2 (ko)
KR (1) KR0139873B1 (ko)

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JP3406949B2 (ja) * 1995-01-31 2003-05-19 キヤノン株式会社 半導体集積回路装置
JPH0951078A (ja) * 1995-05-29 1997-02-18 Mitsubishi Electric Corp 半導体記憶装置および半導体装置
JPH098075A (ja) * 1995-06-23 1997-01-10 Toshiba Corp 半導体装置
US5903034A (en) * 1995-09-11 1999-05-11 Hitachi, Ltd. Semiconductor circuit device having an insulated gate type transistor
JPH1074843A (ja) * 1996-06-28 1998-03-17 Toshiba Corp 多電源集積回路および多電源集積回路システム
US5793069A (en) * 1996-06-28 1998-08-11 Intel Corporation Apparatus for protecting gate electrodes of target transistors in a gate array from gate charging by employing free transistors in the gate array
JPH10223775A (ja) * 1997-01-31 1998-08-21 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
TW329049B (en) * 1997-02-24 1998-04-01 Winbond Electronics Corp The circuit for preventing latch-up the multi-power-on IC
JP3557510B2 (ja) * 1997-06-30 2004-08-25 沖電気工業株式会社 半導体装置
US6107672A (en) * 1997-09-04 2000-08-22 Matsushita Electronics Corporation Semiconductor device having a plurality of buried wells
JP4330183B2 (ja) * 1997-09-30 2009-09-16 株式会社ルネサステクノロジ 半導体記憶装置
JP4295370B2 (ja) * 1998-07-02 2009-07-15 Ｏｋｉセミコンダクタ株式会社 半導体素子
JP3244065B2 (ja) 1998-10-23 2002-01-07 日本電気株式会社 半導体静電保護素子及びその製造方法
JP3337130B2 (ja) * 1999-01-25 2002-10-21 日本電気株式会社 半導体装置
US6411480B1 (en) 1999-03-01 2002-06-25 International Business Machines Corporation Substrate pumped ESD network with trench structure
JP3317345B2 (ja) 1999-07-23 2002-08-26 日本電気株式会社 半導体装置
US6245609B1 (en) * 1999-09-27 2001-06-12 Taiwan Semiconductor Manufacturing Company High voltage transistor using P+ buried layer
DE10134178B4 (de) * 2001-07-13 2006-09-21 Infineon Technologies Ag Halbleiterspeicher mit mehreren Speicherzellenfeldern
US6664608B1 (en) * 2001-11-30 2003-12-16 Sun Microsystems, Inc. Back-biased MOS device
US20030162360A1 (en) * 2002-02-25 2003-08-28 Beasom James D. Reduced mask count buried layer process
TW536802B (en) * 2002-04-22 2003-06-11 United Microelectronics Corp Structure and fabrication method of electrostatic discharge protection circuit
DE10223950B4 (de) * 2002-05-29 2005-08-11 Infineon Technologies Ag MOS-Leistungstransistor
TW548823B (en) * 2002-07-25 2003-08-21 Winbond Electronics Corp ESD protection device coupled between a first high power line and a second high power line
US6870228B2 (en) * 2002-08-07 2005-03-22 Broadcom Corporation System and method to reduce noise in a substrate
DE10255115B3 (de) * 2002-11-26 2004-07-15 Infineon Technologies Ag Ansteuerschaltung für eine Zündpille eines Fahrzeugrückhaltesystems
KR100616057B1 (ko) * 2002-11-29 2006-08-28 가부시끼가이샤 도시바 반도체 집적 회로 장치
JP4318511B2 (ja) * 2003-08-26 2009-08-26 三洋電機株式会社 昇圧回路
JP2005142321A (ja) * 2003-11-06 2005-06-02 Nec Electronics Corp 半導体集積回路装置およびその製造方法
US7723803B2 (en) * 2005-03-07 2010-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Bipolar device compatible with CMOS process technology
US8450672B2 (en) * 2009-06-30 2013-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS image sensors formed of logic bipolar transistors
US9076863B2 (en) * 2013-07-17 2015-07-07 Texas Instruments Incorporated Semiconductor structure with a doped region between two deep trench isolation structures
JP6034268B2 (ja) * 2013-09-13 2016-11-30 株式会社東芝 半導体装置
US9793258B1 (en) * 2016-11-04 2017-10-17 United Microelectronics Corp. Electrostatic discharge device
US10262986B2 (en) * 2017-06-13 2019-04-16 United Microelectronics Corp. Protection device and method for fabricating the protection device

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US5181091A (en) * 1988-04-29 1993-01-19 Dallas Semiconductor Corp. Integrated circuit with improved protection against negative transients

Also Published As

Publication number Publication date
JPH0729987A (ja) 1995-01-31
US5581103A (en) 1996-12-03
JP3246807B2 (ja) 2002-01-15
KR0139873B1 (ko) 1998-08-17

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