KR950001935A - 집적회로 제조방법 - Google Patents

집적회로 제조방법 Download PDF

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KR950001935A
KR950001935A KR1019940014409A KR19940014409A KR950001935A KR 950001935 A KR950001935 A KR 950001935A KR 1019940014409 A KR1019940014409 A KR 1019940014409A KR 19940014409 A KR19940014409 A KR 19940014409A KR 950001935 A KR950001935 A KR 950001935A
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layer
trench
chemical mechanical
policy
coplanar
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KR1019940014409A
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말콤 보이드 존
폴 엘룰 죠셉
핀 타이 싱
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존 이.모울
노오던 텔레콤 리미티드
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Publication of KR950001935A publication Critical patent/KR950001935A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

집적 회로용 반도체 기판에 예를 들어, 트렌치 분리 필드 산화물 영역 또는 박막 반도체 디바이스들이 형성되는 트렌치 분리 반도체 영역과 같은 완전 평탄화된 트렌지 분리 영역을 형성하는 방법이 제공된다. 평탄화는 넓은 트랜체들의 중앙 영역 뿐만 아니라 트렌치들에 인접한 반도체 기판 표면에 화학 기계적 폴리시 저항 재료의 동일 평면성 층들이 제공되는 화학 기계적 폴리싱 공정에 의해 달성된다. 화학 기계적 폴리시 저항층은 화학 기계적 폴리싱에 의한 전체적인 웨이퍼 평탄화 동안 트렌치 충전층들의 디싱을 방지하기 위해 넓은 트렌치의 중앙영역에 에치 스톱을 형성한다. 이 방법은 서브미크론 VLSI 및 ULSI 집적 회로구조용 CMOS, 바이폴라 및 바이폴라 CMOS 공정들에 적합하다.

Description

집적회로 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 제1실시예에 따른 트렌치 분리 영역을 형성하는 연속 단계들에서 부분적으로 제조된 집적 회로 구조의 개략적인 부분 단면도.

Claims (6)

  1. 집적 회로 제조 방법에 있어서, 평탄한 표면을 갖고, 화학 기계적 폴리시 저항 재료의 표면층을 포함하며, 그 안에 측면이 급경사인 트렌치들이 한정된 반도체 기판을 제공하는 단계; 적어도 1개의 트렌치 충전 재료의 공형층(conformal layer) 및 반도체 기판의 화학 기계적 폴리시 저항 재료의 표면층과 표면 동일 평면성(surface coplanar)를 폴리시 스톱(polish stop)을 트렌치의 중앙 영역에 제공하는 화학 기계적 폴리시 저항 재료의 공형층으로 트렌치를 충전시키는 단계; 및 최종 구조를 화학 기계적 폴리싱에 의해 평탄화시켜, 기판의 평탄화 표면 및 트렌치의 중앙 영역이 폴리시 스톱인 동일 평면성 표면 위로 연장한 층들을 선택적으로 제거하는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  2. 제1항에 있어서, 트렌치의 중앙 영역에 기판의 화학 기계적 폴리시 저항 재료의 표면층의 두께와 동일한 두께를 갖는 폴리시 스톱을 형성하는 화학 기계적 폴리시 저항 재료층을 제공하는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  3. 집적 회로 제조 방법에 있어서, 표면, 이 표면 위에 형성된 화학 기계적 폴리시 스톱층 및 오버라잉(overlying) 유전체층을 갖고 있고, 그 안에 측면이 급경사인 트렌치들이 한정된 반도체 기판을 제공하는 단계; 두께가 반도체 기판의 표면과 동일 평면성인 트렌치의 중앙을 충전하기에 충분한 정도의 트렌치 충전 재료의 공형층을 트렌치에 인접한 제1유전체층의 표면위로 전체적으로 연장하도록 제공하고 트렌치를 충전하는 단계; 기판 표면상의 제1폴리시 스톱층의 부분들과 트렌치 중앙의 제2폴리시 스톱층의 부분의 표면들이 동일 평면성이 되도록 제2화학 기계적 폴리시 스톱층인 오버라잉 공형층을 전체적으로 제공하는 단계; 및 제2유전체층들 및 반도체 기판의 표면과 동일 평면성인 제1 및 제2폴리시 스톱층의 부분들의 표면들 위로 연장한 제2폴리시 스톱층을 선택적으로 제거함으로써 최종 구조를 평탄화시키는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  4. 제3항에 있어서, 기판 표면과 동일 평면성인 완전 평탄화된 표면을 남기도록 폴리시 저항층들을 선택적으로 제거하는 후속 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  5. 제3항에 있어서, 상기 공형 트렌치 충전층을 제공하는 단계가 평탄화 단계후에, 트렌치 분리 반도체 웰 영역이 제공되도록 유전체 재료의 제1공형층을 피착하고 그 다음으로, 반도체 재료의 제2공형층을 피착하는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  6. 제5항에 있어서, 폴리시 저항 층들을 연속적으로 제거하여 기판 표면과 동일 평면성인 완전평탄화된 표면을 남기는 단계; 트렌치 분리 반도체 웰 영역의 동일 평면성 표면 및 반도체 기판에 MOS트랜지스터의 소소, 드레인 및 채널 영역을 한정하는 단계; 게이트 유전체 재료층을 전체적으로 형성하는 단계; 및 도전성 재료의 오버라잉층을 형성하고, 유전체 재료층에 의해 채널 영역 위에 분리 배치된 도전성 재료에 게이트 전극들을 한정하는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940014409A 1993-06-24 1994-06-23 집적회로 제조방법 KR950001935A (ko)

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US08/080,544 US5362669A (en) 1993-06-24 1993-06-24 Method of making integrated circuits
US08/080,544 1993-06-24

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KR950001935A true KR950001935A (ko) 1995-01-04

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JP (1) JPH0799237A (ko)
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