KR940010207A - 반도체 소자 제조방법 - Google Patents

반도체 소자 제조방법 Download PDF

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Publication number
KR940010207A
KR940010207A KR1019930019633A KR930019633A KR940010207A KR 940010207 A KR940010207 A KR 940010207A KR 1019930019633 A KR1019930019633 A KR 1019930019633A KR 930019633 A KR930019633 A KR 930019633A KR 940010207 A KR940010207 A KR 940010207A
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South Korea
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metal
insulating layer
opening
layer
semiconductor device
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KR1019930019633A
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English (en)
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KR0182299B1 (ko
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지바 마이클
카츠 아비샤이
Original Assignee
디. 아이. 카프란
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR940010207A publication Critical patent/KR940010207A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2233—Diffusion into or out of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/11—Metal-organic CVD, ruehrwein type

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

반도체 소자 기판(10, 11)은 주변을 가지며 그위에 이산화 실리콘등의 절연층(12)이 위치하는데, 이 절연층은 주면까지 이어지는 개구를 가지며, 아연 도핑 텅스텐 등의 불순물 도핑 플럭(13)이 금속 열적 사이클 저압 금속 유기적 화학적 증착(RTC-LP-MOCVD)처리에 의해 상기 절연층내의 개구의 높이 보다 훨씬 이하 높이의 플럭이 있도록 한 두께로 상기 개구내에 공간 선택적으로 용착되며, 텅스텐 등의 순수 전기 전도 장벽 금속으로 이루어진 다른 플럭(14)이 불순물 도핑 플럭의 적어도 전체 상면과 상기 절연층의 측벽상에 용착되며, 그후 하부의 반도체 소자 기판에 불순물을 확산시키도록 제조되는 구조물이 가열될 수 있다. 티타늄/플래티늄/금 등의 금속화층(15)이 순수전도 장벽 금속상에 용착될 수 있으며, 소자에 소정의 액세스 금속화를 제공하도록 패턴화될 수 있다.

Description

반도체 소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도면은 본 발명의 특정 실시예에 따라 제조된 반도체 소자의 일부분에 대한 정단면도.

Claims (5)

  1. 반도체 소자제조 방법으로서, (a)주표면을 가지는 반도체 본체(10, 11)를 제공하는 단계; (b)주표면의 적어도 한부분상에 그 내부의 적어도 하나의 개구를 제외하고 균일한 두께의 절연층을 형성하는 단계; (c)금속 열적사이클의 저압 금속 유기적(metal organic) 화학적 증착에 의해 상기 절연층 두께 이하의 규정의 두께로 상기 개구내에 선택적으로 제1금속층(13)을 공간 선택적으로 용착시키는 단계를 포함하는데, 상기 금속층은 제1금속 및 불순물을 포함하며, 상기 불순물은 용착 금속층으로 부터 반도체 본체로의 확산에 제 1금속보다 상당히 큰 경향을 가지며 ; (d)화학적 증착에 의해 상기 개구내의 제1금속층의 적어도 모든 곳에 제2금속층(14)을 공간 선택적으로 용착시키는 단계를 포함하는데, 상기 제2금속층은 불순물이 아닌 제2금속을 포함하며, 그를 통하는 불순물을 확산을 억제하는 성질을 가지는 것을 특징으로 하는 반도체 소자 제조 방법.
  2. 제1항에 있어서, 상기 단계(d)는 절연층의 적어도 한 부분과 상기 제2금속성층 상에 제3금속성층(15)을 형성하는 단계를 추가로 포함하는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, 상기 제1 및 제2 금속은 동일한 소자인 것을 특징으로 하는 방법.
  4. 제3항에 있어서, 상기 제1 및 제2금속은 기본적으로 텅스텐이며, 상기 불순물은 기본적으로 아연인 것을 특징으로 하는 방법.
  5. 제1항, 2항, 3항 또는 제4항에 있어서, 단계(c) 및 단계(d)는 단일 융착실에서 수행되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930019633A 1992-10-13 1993-09-24 반도체 소자 제조방법 KR0182299B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US960,526 1992-10-13
US07/960,526 US5232873A (en) 1992-10-13 1992-10-13 Method of fabricating contacts for semiconductor devices

Publications (2)

Publication Number Publication Date
KR940010207A true KR940010207A (ko) 1994-05-24
KR0182299B1 KR0182299B1 (ko) 1999-04-15

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US (1) US5232873A (ko)
EP (1) EP0597587A1 (ko)
JP (1) JP3583451B2 (ko)
KR (1) KR0182299B1 (ko)
SG (1) SG44490A1 (ko)
TW (1) TW295681B (ko)

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JP2773578B2 (ja) * 1992-10-02 1998-07-09 日本電気株式会社 半導体装置の製造方法
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KR960008558B1 (en) * 1993-03-02 1996-06-28 Samsung Electronics Co Ltd Low resistance contact structure and manufacturing method of high integrated semiconductor device
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US5599739A (en) * 1994-12-30 1997-02-04 Lucent Technologies Inc. Barrier layer treatments for tungsten plug
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JP3000877B2 (ja) * 1995-02-20 2000-01-17 松下電器産業株式会社 金メッキ電極の形成方法、基板及びワイヤボンディング方法
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US6239028B1 (en) * 1998-09-03 2001-05-29 Micron Technology, Inc. Methods for forming iridium-containing films on substrates
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US6329286B1 (en) 1999-04-27 2001-12-11 Micron Technology, Inc. Methods for forming conformal iridium layers on substrates
US6660631B1 (en) * 2000-08-31 2003-12-09 Micron Technology, Inc. Devices containing platinum-iridium films and methods of preparing such films and devices
KR100707882B1 (ko) * 2005-12-14 2007-04-13 삼성전자주식회사 선택적 에피택시얼 성장 방법
JP5244814B2 (ja) * 2006-11-22 2013-07-24 ソイテック 化学気相成長チャンバ用の温度制御されたパージゲート弁を使用した方法、アセンブリ及びシステム
US9190320B2 (en) * 2012-01-26 2015-11-17 Applied Materials, Inc. Devices including metal-silicon contacts using indium arsenide films and apparatus and methods

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JPS60130165A (ja) * 1983-12-16 1985-07-11 Fujitsu Ltd 半導体装置
US4843033A (en) * 1985-09-27 1989-06-27 Texas Instruments Incorporated Method for outdiffusion of zinc into III-V substrates using zinc tungsten silicide as dopant source
JPH0288452A (ja) * 1988-09-26 1990-03-28 Nichias Corp 耐熱性無機質成形体
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US5158896A (en) * 1991-07-03 1992-10-27 International Business Machines Corporation Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions

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Publication number Publication date
EP0597587A1 (en) 1994-05-18
TW295681B (ko) 1997-01-11
JPH06224409A (ja) 1994-08-12
SG44490A1 (en) 1997-12-19
US5232873A (en) 1993-08-03
JP3583451B2 (ja) 2004-11-04
KR0182299B1 (ko) 1999-04-15

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