KR940006254A - 수지용 인서트 부재 - Google Patents

수지용 인서트 부재 Download PDF

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Publication number
KR940006254A
KR940006254A KR1019930012249A KR930012249A KR940006254A KR 940006254 A KR940006254 A KR 940006254A KR 1019930012249 A KR1019930012249 A KR 1019930012249A KR 930012249 A KR930012249 A KR 930012249A KR 940006254 A KR940006254 A KR 940006254A
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KR
South Korea
Prior art keywords
insert member
resin
nickel
plating
containing alloy
Prior art date
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KR1019930012249A
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English (en)
Inventor
도시히꼬 시마다
Original Assignee
이노우에 사다오
신꼬오 덴기 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 이노우에 사다오, 신꼬오 덴기 고오교오 가부시끼가이샤 filed Critical 이노우에 사다오
Publication of KR940006254A publication Critical patent/KR940006254A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12014—All metal or with adjacent metals having metal particles
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12014—All metal or with adjacent metals having metal particles
    • Y10T428/12028—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, etc.]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

인서트부재에 가공변형등을 잔류시키지 않고 용이하게 봉지수지와의 밀착성을 향상시킬 수 있는 수지용 인서트 부재를 제공한다. 적어도 일부가 수지중에 봉입되는 금속제의 인서트부재에 있어서 상기 인서트부재의 수지중에 봉입되는 부분의 표면이 도금에 의해서 형성된 다수의 반구상의 입상체로 된

Description

수지용 인서트 부재
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 있어서 금속표면에 하지도금을 행함으로써 형성된 금속입자구조를 나타낸 전자현미경 사진,
제2도는 제1도에 나타낸 금속입자가 형성된 금속표면에 도금두께가 0.5㎛가 되도록 니켈 함유 합금도금을 행함으로써 형성된 금속입자구조를 나타낸 전자현미경 사진,
제3도는 제1도에 나타낸 금속입자가 형성된 금속표면에 도금두께가 1㎛가 되도록 니켈함유 합금도금을 행함으로써 형성된 금속입자구조를 나타낸 전자현미경 사진,
제5도는 본 발명에 채용되는 리드프레임을 나타낸 평면도.

Claims (5)

  1. 적어도 일부가 수지중에 봉입되는 금속제의 인서트부재에 있어서, 상기 인서트부재의 수지중에 봉입되는 부분의 표면이 도금에 의해서 형성된 다수의 반구상의 입상체로 된면으로 형성되어 있는 것을 특징으로 하는 수지용 인서트 부재.
  2. 제1항에 있어서, 상기 인서트부재의 수지중에 봉입되는 부분의 표면에 하지도금으로서 동도금이 조면상으로 행해지고 또 상기 하지도금위에 니켈단독 또는 니켈함유 합금도금이 행해져 있는 수지용 인서트부재.
  3. 제1 또는 제2항에 있어서, 상기 금속제의 인서트 부재가 동제인 수지용 인서트 부재.
  4. 제2항에 있어서, 상기 니켈단독 또는 니켈 함유 합금의 도금두께가 0.5 ~ 1.5㎛인 수지용 인서트 부재.
  5. 제2또는 제4항에 있어서, 상기 니켈함유 합금이 니켈-석 합금인 수지용 인서트 부재.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930012249A 1992-07-11 1993-07-01 수지용 인서트 부재 KR940006254A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20748092A JP3228789B2 (ja) 1992-07-11 1992-07-11 樹脂用インサート部材の製造方法
JP92-207480 1992-07-11

Publications (1)

Publication Number Publication Date
KR940006254A true KR940006254A (ko) 1994-03-23

Family

ID=16540451

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930012249A KR940006254A (ko) 1992-07-11 1993-07-01 수지용 인서트 부재

Country Status (6)

Country Link
US (1) US5585195A (ko)
EP (1) EP0579464B1 (ko)
JP (1) JP3228789B2 (ko)
KR (1) KR940006254A (ko)
DE (1) DE69318894T2 (ko)
SG (1) SG46235A1 (ko)

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US6055140A (en) 1997-07-25 2000-04-25 Seagate Technology, Inc. Rigid disc plastic substrate with high stiffness insert
US6141870A (en) 1997-08-04 2000-11-07 Peter K. Trzyna Method for making electrical device
JPH11189835A (ja) * 1997-12-25 1999-07-13 Jst Mfg Co Ltd すず−ニッケル合金およびこの合金により表面処理を施した部品
US6509632B1 (en) 1998-01-30 2003-01-21 Micron Technology, Inc. Method of fabricating a redundant pinout configuration for signal enhancement in an IC package
US6683368B1 (en) 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
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US6551859B1 (en) * 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
JP2002299538A (ja) * 2001-03-30 2002-10-11 Dainippon Printing Co Ltd リードフレーム及びそれを用いた半導体パッケージ
JP3841768B2 (ja) 2003-05-22 2006-11-01 新光電気工業株式会社 パッケージ部品及び半導体パッケージ
US7049683B1 (en) 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
DE10348715B4 (de) * 2003-10-16 2006-05-04 Infineon Technologies Ag Verfahren zum Herstellen eines Flachleiterrahmens mit verbesserter Haftung zwischen diesem und Kunststoff sowie Flachleiterrahmen
US7095096B1 (en) 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
KR20060030356A (ko) * 2004-10-05 2006-04-10 삼성테크윈 주식회사 반도체 리이드 프레임과, 이를 포함하는 반도체 패키지와,이를 도금하는 방법
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
KR101241735B1 (ko) 2008-09-05 2013-03-08 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
US8110500B2 (en) * 2008-10-21 2012-02-07 International Business Machines Corporation Mitigation of plating stub resonance by controlling surface roughness
KR20100103015A (ko) * 2009-03-12 2010-09-27 엘지이노텍 주식회사 리드 프레임 및 그 제조방법
KR101113891B1 (ko) 2009-10-01 2012-02-29 삼성테크윈 주식회사 리드 프레임 및 리드 프레임 제조 방법
KR101385887B1 (ko) 2009-11-09 2014-04-15 스미도모쥬기가이고교 가부시키가이샤 크라이오펌프, 및 진공배기방법
JP5553638B2 (ja) * 2010-02-19 2014-07-16 住友重機械工業株式会社 コールドトラップ、及び真空排気装置
JP6366032B2 (ja) * 2013-11-29 2018-08-01 大口マテリアル株式会社 リードフレームおよびその製造方法
JP6345342B2 (ja) * 2015-04-15 2018-06-20 三菱電機株式会社 半導体装置
KR102529295B1 (ko) 2015-11-05 2023-05-08 후루카와 덴키 고교 가부시키가이샤 리드 프레임재 및 그 제조방법
DE102016117841A1 (de) 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung
JP6479265B2 (ja) 2016-12-27 2019-03-06 古河電気工業株式会社 リードフレーム材およびその製造方法ならびに半導体パッケージ
JP7014695B2 (ja) 2018-10-18 2022-02-01 Ｊｘ金属株式会社 導電性材料、成型品及び電子部品
JP6805217B2 (ja) 2018-10-18 2020-12-23 Ｊｘ金属株式会社 導電性材料、成型品及び電子部品

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Also Published As

Publication number Publication date
DE69318894D1 (de) 1998-07-09
JP3228789B2 (ja) 2001-11-12
EP0579464B1 (en) 1998-06-03
DE69318894T2 (de) 1998-09-24
JPH0629439A (ja) 1994-02-04
EP0579464A2 (en) 1994-01-19
EP0579464A3 (ko) 1994-03-23
US5585195A (en) 1996-12-17
SG46235A1 (en) 1998-02-20

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