JPS5730355A - Plating structure for semiconductor material - Google Patents

Plating structure for semiconductor material

Info

Publication number
JPS5730355A
JPS5730355A JP10475080A JP10475080A JPS5730355A JP S5730355 A JPS5730355 A JP S5730355A JP 10475080 A JP10475080 A JP 10475080A JP 10475080 A JP10475080 A JP 10475080A JP S5730355 A JPS5730355 A JP S5730355A
Authority
JP
Japan
Prior art keywords
layer
crystalline grains
plating
pellet
rough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10475080A
Other languages
Japanese (ja)
Inventor
Shozo Hayashi
Yoshiaki Miyaoka
Toshihito Nishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP10475080A priority Critical patent/JPS5730355A/en
Publication of JPS5730355A publication Critical patent/JPS5730355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/325Material
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/491Disposition
    • H01L2224/4912Layout
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    • H01L2224/732Location after the connecting process
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    • H01L2224/838Bonding techniques
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    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Abstract

PURPOSE:To enhance the bonding strength of a member to be soldered and plating layers, one of which is made of dense crystalline grains and the other of which is made of rough crystalline grains and to improve the adherence by forming the one plating layer made of the dense crystalline grains and the other plating layer made of rough crystalline grains at the part to be soldered of a semiconductor material. CONSTITUTION:Gold or silver is plated on a base material (a), the primary plating layer 2 having crystalline grains of the same degree as the conventional one is formed, and the secondary plating layer 3 having rough crystalline grains is formed on the layer 2 by varying the plating conditions from the those at the time of plating the layer 2 in such a manner that the total thickness of the primary and secondary plating layers is at least more than 2mum and the layer 2 is thinner by one- several-th of the layer 2. A solder pellet (c) is placed on the layer, a silicon chip 4 is placed on the pellet (c), and a gold wire 6 is connected to the lead 1 via a pad 5. Since the crystalline grains are large, the expanding property of the molten pellet is improved due to the capillary action, the pellet is thus intimately contacted, and the bonding strength can be increased.
JP10475080A 1980-07-29 1980-07-29 Plating structure for semiconductor material Pending JPS5730355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10475080A JPS5730355A (en) 1980-07-29 1980-07-29 Plating structure for semiconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10475080A JPS5730355A (en) 1980-07-29 1980-07-29 Plating structure for semiconductor material

Publications (1)

Publication Number Publication Date
JPS5730355A true JPS5730355A (en) 1982-02-18

Family

ID=14389163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10475080A Pending JPS5730355A (en) 1980-07-29 1980-07-29 Plating structure for semiconductor material

Country Status (1)

Country Link
JP (1) JPS5730355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0579464A2 (en) * 1992-07-11 1994-01-19 Shinko Electric Industries Co. Ltd. Metal insert and a surface roughening treatment method for it

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0579464A2 (en) * 1992-07-11 1994-01-19 Shinko Electric Industries Co. Ltd. Metal insert and a surface roughening treatment method for it
EP0579464A3 (en) * 1992-07-11 1994-03-23 Shinko Electric Ind Co
US5585195A (en) * 1992-07-11 1996-12-17 Shinko Electric Industries Company, Limited Metal insert and rough-surface treatment method thereof

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