KR940002980A - 반도체 칩 실장방법 및 기판 구조체 - Google Patents

반도체 칩 실장방법 및 기판 구조체 Download PDF

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Publication number
KR940002980A
KR940002980A KR1019920013308A KR920013308A KR940002980A KR 940002980 A KR940002980 A KR 940002980A KR 1019920013308 A KR1019920013308 A KR 1019920013308A KR 920013308 A KR920013308 A KR 920013308A KR 940002980 A KR940002980 A KR 940002980A
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South Korea
Prior art keywords
substrate
hole
chip
pad
wiring network
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KR1019920013308A
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English (en)
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KR950012658B1 (ko
Inventor
김구성
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김광호
삼성전자 주식회사
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Priority to KR1019920013308A priority Critical patent/KR950012658B1/ko
Priority to JP5180088A priority patent/JP2592038B2/ja
Priority to US08/095,375 priority patent/US5407864A/en
Publication of KR940002980A publication Critical patent/KR940002980A/ko
Application granted granted Critical
Publication of KR950012658B1 publication Critical patent/KR950012658B1/ko

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

연결패드가 형성된 반도체 칩과, 상기 연결캐드와 대응하는 위치에 관통공이 있고 적어도 2층 이상의 절연기판과, 그 사이의 도전 배선망이 있는 다층기판과를 상호 연결함에 있어, 상기 칩 패드 위치에 대응하는 위치에서 홀을 형성하고 있는 필름 타입의 절연접착층을 칩과 기판관에 개재시켜 칩의 패드, 필름의 흘, 기판의 관통공이 서로 일치하도록 정렬시켜 칩과 기판을 부착시키는 단계와, 칩이 부착된 기판의 상면의 반대측 뒷면에서 관통공의 한쪽을 막고 있는 칩의 금속패드와 관통공 내벽 및 기판 뒷면을 도포하도록 도전층을 형성하여 칩의 패드와 기판 내부의 도면 배선망이 상호 연결되도록 하는 단계와, 관통공을 절연물질로 매립하는 단계로 이루어져 칩을 기판에 실장하도록 하는 것을 특징으로 하는 반도체 칩 실장방법에 관한 것.

Description

반도체 칩 실장방법 및 기판 구조체
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(a)-(e)는 본 발명에 따른 반도체 칩 실장방식을 설명하는 조립 공정도이다.

Claims (11)

  1. 연결패드가 형성된 반도체 칩과, 상기 연결패드와 대응하는 위치에 관통공이 있고 이 관통공에 연결된 도전 배선망이 있는 기판을 상호 연결함에 있어, 상기 칩 패드 위치에 대응하는 위치에서 홀을 형성하고 있는 필름 타입의 절연접착층을 칩과 기판간에 개재시켜 칩의 패드, 필름의 홀, 기판의 관통공이 서로 일치하도록 정렬시켜 칩과 기판을 부착시키는 단계와, 칩이 부착된 기판의 상면의 반대측 뒷면에서 관통공의 한쪽을 막고 있는 칩의 금속패드와 관통공 내벽 및 기판 뒷면을 도포하도록 도전층을 형성하여 칩의 패드와기판 내부로 도전 배선망이 상호 연결되도록 하는 단계와, 관통공을 절연물질로 매립하는 단계로 이루어지며 절연기판 뒷면을 폴리슁하여 칩을 기판에 실장하도록 하는 것을 특징으로 하는 반도체 칩 실장방법.
  2. 제1항에 있어서, 상기 관통공이 있는 기판은 적어도 2층이상의 절연기판과 그 사이에 도전 배선망이 있는 다층기판인 것을 특징으로 하는 반도체 칩 실장방법.
  3. 제1항에 있어서, 상기 관통공이 있는 기판은 기판 표면에 상기 관통공이 연결된 도전 배선망이 있는 기판인 것을 특징으로 하는 반도체 칩 실장방법.
  4. 제1항에 있어서, 상기 도전층은 스퍼터링, 전기도금 또는 증착(evaporation)에 의해 Au 내지는 Ni로 형성됨을 특징으로 하는 반도체 칩 실장방법.
  5. 제1항에 있어서, 상기 관통공을 매립하고 있는 절연물질은 에폭시 또는 폴리이미드인 것을 특징으로 하는 반도체 칩 실장방법.
  6. 표면에 연결패드가 있는 반도체층과 상기 패드와 같은 위치에 형성된 관통공과 이 관통공에 연결된 도전 배선망을 포함하는 기판과, 상기 칩의 패드와 기판의 관통공을 일치시키면서 그 사이에 개재된 접착층과, 상기 기판의 관통 내벽과 칩의 패드 표면에 형성되어, 상기 기판 내부의 도전 배선망을 반도체 칩의 패드와 연결하고 있는 도전층과, 관통공을 매립하고 상기 도전층상에 형성된 절연층으로 구성됨을 특징으로 하는 반도체 칩이 결합된 기판 구조체.
  7. 제4항에 있어서, 상기 관통공 내의 도전층은 Au 또는 Ni로부터 이루어진 것을 특징으로 하는 반도체 칩이 결합된 기판 구조체.
  8. 제4항에 있어서, 상기 관통공을 매립하고 있는 절연물질은 에폭시 또는 폴리아미드인 것을 특징으로 하는 반도체 칩이 결합된 기판 구조체.
  9. 제7항에 있어서, 절연기판 뒷면을 폴리슁하여 된 것을 특징으로 하는 기판 구조체.
  10. 제4항에 있어서, 상기 관통공이 있는 기판은 직어도 2층 이상의 절연기판과 그 사이에 도전 배선망이 있는 다층기판인 것을 특징을 하는 기판 구조체.
  11. 제4항에 있어서, 상기 관통공이 있는 기판은 기판표면에 상기 관통공이 연결된 도전 배선망이 있는 기판인 것을 특징으로 하는 기판 구조체.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019920013308A 1992-07-24 1992-07-24 반도체 칩 실장방법 및 기판 구조체 KR950012658B1 (ko)

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KR1019920013308A KR950012658B1 (ko) 1992-07-24 1992-07-24 반도체 칩 실장방법 및 기판 구조체
JP5180088A JP2592038B2 (ja) 1992-07-24 1993-07-21 半導体チップ実装方法および基板構造体
US08/095,375 US5407864A (en) 1992-07-24 1993-07-23 Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip

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KR1019920013308A KR950012658B1 (ko) 1992-07-24 1992-07-24 반도체 칩 실장방법 및 기판 구조체

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