KR940001773A - 다층 인쇄배선판 및 그 제조방법 - Google Patents
다층 인쇄배선판 및 그 제조방법Info
- Publication number
- KR940001773A KR940001773A KR1019930010533A KR930010533A KR940001773A KR 940001773 A KR940001773 A KR 940001773A KR 1019930010533 A KR1019930010533 A KR 1019930010533A KR 930010533 A KR930010533 A KR 930010533A KR 940001773 A KR940001773 A KR 940001773A
- Authority
- KR
- South Korea
- Prior art keywords
- wiring board
- printed wiring
- substrate
- hybrid
- modulus
- Prior art date
Links
Classifications
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- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
- A47J43/00—Implements for preparing or holding food, not provided for in other groups of this subclass
- A47J43/04—Machines for domestic use not covered elsewhere, e.g. for grinding, mixing, stirring, kneading, emulsifying, whipping or beating foodstuffs, e.g. power-driven
- A47J43/07—Parts or details, e.g. mixing tools, whipping tools
- A47J43/0716—Parts or details, e.g. mixing tools, whipping tools for machines with tools driven from the lower side
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
- A47J43/00—Implements for preparing or holding food, not provided for in other groups of this subclass
- A47J43/04—Machines for domestic use not covered elsewhere, e.g. for grinding, mixing, stirring, kneading, emulsifying, whipping or beating foodstuffs, e.g. power-driven
- A47J43/07—Parts or details, e.g. mixing tools, whipping tools
- A47J43/08—Driving mechanisms
- A47J43/085—Driving mechanisms for machines with tools driven from the lower side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Food Science & Technology (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
전자부품의 실장용량을 증대시킨 구조로 한 것으로서 내층기판(1)의 본딩랜드(13)에 하이브리드 모듀울(14),(15)를 다이본딩힌후 하이브리드 모듀울(14), (15)를 끼우도록 외층기판(2),(3)을 적층하고, 외층기판(2)(3)에 접속구멍(21), (22)를 형성한후 도금처리해서 하이브리드 모듀울(14),(15)와 외층기판(2),(3)을 전기적으로 접속하고, 하이브리드 모듀울(14),(15)는 저항기 콘덴서, 반도체 칩등의 전자부품을 배치하고 있고, 적층기판 내부에 전자부품을 매설한 상태로 실장시킨 것과 동등한 구조로 해서 적층기판의 외면에 전자부품을 실장시키는데 추가하여 내부에 전자부품을 실장시키기 때문에 실장용량이 증대된 다층 인쇄배선판 및 그 제조방법이다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본발명의 1실시예의 제조공정의 블록도.
제5도는 접속구멍 형성을 나타내는 단면도.
제6도는 도긍층 피복을 나타내는 단면도.
제7도는 회로형성을 나타내는 단면도.
제8도는 제조된 다층 인쇄 배선판의 단면도.
Claims (3)
- 전자부품 기능을 구비한 하이브리드 모듀울(14),(15)가 하나의 인쇄 배선판에 다이본딩 됨과 동시에, 상기 한 하이브리드 모듀울(14),(15)를 끼우도록 적어도 1매의 다른 인쇄배선판이 상기한 하나의 인쇄 배선판에 적층되는 것을 특징으로 하는 다층 인쇄 배선판.
- 제1항에 있어서, 상기한 하이브리드 모듀울(14),(15)은 저항기 콘덴서 및 반도체 칩중의 적어도 하나가 망을 형성하도록 세라믹 기판에 배치된 것을 특징으로 하는 다층인쇄 배선판.
- 전자부품 기능을 구비한 하이브리드 모듀울(14),(15)를 회로가 형성된 하나의 기판에 다이 본딩하는 공정과, 상기한 하나의 기판상에 적어도 1매의 다른 기판을 적층한후 적어도 하이브리드 모듀울(14),(15)의 랜드에 대응하는 부분을 제거 해서 접속구멍(21)-(25)을 형성하는 공정과, 이 접속구멍(21)-(25)를 거쳐서 하이브리드 모듀울(14),(15)와 다른 기판과를 도통상태로 하는 공정과를 구비하고 있는 것을 특징으로 하는 다층 인쇄 배선판의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04173798A JP3086332B2 (ja) | 1992-06-08 | 1992-06-08 | 多層プリント配線板の製造方法 |
JP92-173798 | 1992-06-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940001773A true KR940001773A (ko) | 1994-01-11 |
Family
ID=15967358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930010533A KR940001773A (ko) | 1992-06-08 | 1992-06-18 | 다층 인쇄배선판 및 그 제조방법 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0574207A3 (ko) |
JP (1) | JP3086332B2 (ko) |
KR (1) | KR940001773A (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP4851652B2 (ja) * | 2000-02-09 | 2012-01-11 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
JP2002111222A (ja) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | 多層基板 |
FI20041525A (fi) * | 2004-11-26 | 2006-03-17 | Imbera Electronics Oy | Elektroniikkamoduuli ja menetelmä sen valmistamiseksi |
KR100867038B1 (ko) | 2005-03-02 | 2008-11-04 | 삼성전기주식회사 | 커패시터 내장형 인쇄회로기판 및 그 제조방법 |
KR100716824B1 (ko) * | 2005-04-28 | 2007-05-09 | 삼성전기주식회사 | 하이브리드 재료를 이용한 커패시터 내장형 인쇄회로기판및 그 제조방법 |
DE102005032489B3 (de) | 2005-07-04 | 2006-11-16 | Schweizer Electronic Ag | Leiterplatten-Mehrschichtaufbau mit integriertem elektrischem Bauteil und Herstellungsverfahren |
JP2007335675A (ja) * | 2006-06-15 | 2007-12-27 | Fuji Electric Systems Co Ltd | 電源装置および電源装置の製造方法 |
JP2007165932A (ja) * | 2007-02-22 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 多層基板 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USH416H (en) * | 1981-08-31 | 1988-01-05 | Rogers Corporation | High capacitance flexible circuit |
JPH01207992A (ja) * | 1988-02-16 | 1989-08-21 | Hitachi Ltd | 回路配線板 |
JPH02164096A (ja) * | 1988-12-19 | 1990-06-25 | Matsushita Electric Ind Co Ltd | 多層電子回路基板とその製造方法 |
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1992
- 1992-06-08 JP JP04173798A patent/JP3086332B2/ja not_active Expired - Fee Related
- 1992-06-18 KR KR1019930010533A patent/KR940001773A/ko not_active Application Discontinuation
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1993
- 1993-06-04 EP EP19930304382 patent/EP0574207A3/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH05343856A (ja) | 1993-12-24 |
JP3086332B2 (ja) | 2000-09-11 |
EP0574207A3 (en) | 1994-01-12 |
EP0574207A2 (en) | 1993-12-15 |
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