KR930020618A - 반도체 칩에 대한 전기적 접착 방법 및 반도체 장치 - Google Patents

반도체 칩에 대한 전기적 접착 방법 및 반도체 장치 Download PDF

Info

Publication number
KR930020618A
KR930020618A KR1019930003127A KR930003127A KR930020618A KR 930020618 A KR930020618 A KR 930020618A KR 1019930003127 A KR1019930003127 A KR 1019930003127A KR 930003127 A KR930003127 A KR 930003127A KR 930020618 A KR930020618 A KR 930020618A
Authority
KR
South Korea
Prior art keywords
major surface
hole
adhesive pad
pad array
insulating material
Prior art date
Application number
KR1019930003127A
Other languages
English (en)
Other versions
KR100288405B1 (ko
Inventor
이 푸츠 하롤드
Original Assignee
엘.에이취.번바움
아메리칸 텔리폰 앤드 텔리그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘.에이취.번바움, 아메리칸 텔리폰 앤드 텔리그라프 캄파니 filed Critical 엘.에이취.번바움
Publication of KR930020618A publication Critical patent/KR930020618A/ko
Application granted granted Critical
Publication of KR100288405B1 publication Critical patent/KR100288405B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

테이프 자동접착(TAB)기술을 이용하는 장치 제조방법 및 결과를 구조물을 개시한다. 여기서, 통공(30)은 폴리이미드와 같은 절연층(11)을 통해 형성되어, 전도성 핑거(12)가 상기 층의 일표면상에 형성될때 전기도금된다. 그후 결과의 구조는 전도성 핑거가 제공된 표면과 반대쪽에 있는 절연층 표면상에 형성된 전도성 패드(20)에 의해 반도체 칩(41)에 접착된다.

Description

반도체 칩에 대한 전기적 접착 방법 및 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시시예에 따른 장치의 평면도.
제2도는 제1도에 도시한 장치의 저면도.
제3도는 제1도에 도시한 장치의 일부분에 대한 확대 단면도.
제4도는 제1도의 장치를 포함한 본 발명에 따른 조립체의 단면도.

Claims (24)

  1. 가요성 절연물질의 층(11)을 제공하는 단계와, 상기 층을 통해 제1주표면에서 제2주요표면까지 연장되는 통공(30)을 형성하는 단계를 포함하는 반도체 칩(41)에 대한 전기적 접착방법에 있어서, 상기 제1주표면상에 다수의 전도성 핑거(12)를 도금함으로써 상기 전도성 물질이 상기 통공을 통해 연장되어 상기 통공의 상기 끝에 있는 상기 제2주표면상의 제1접착패드 어레이(20)를 형성케 하는 단계와, 상기 제1접착패드 어레이를 상기 반도체 칩의 표면상에 형성된 제2접착패드 어레이에 전기적으로 접착시키는 것을 특징으로 하는 반도체 칩에 대한 전기적 접착 위한 방법.
  2. 제1항에 있어서, 상기 절연물질이 폴리이미드를 포함하는 방법.
  3. 제1항에 있어서, 상기 통공이 레이저 천공에 의해 형성되는 방법.
  4. 제1항에 있어서, 도금에 앞서, 절연물질의 상기 표면들을 에칭하여 상기 전도성 물질을 접착을 개선하는 방법.
  5. 제4항에 있어서, 도금하고 에칭하기에 앞서, 상기 절연물질을 무전해 도금용액에 노출시켜서 양쪽 주표면 및 상기 통공의 벽에 얇은 제1금속 층(22)을 형성하는 방법.
  6. 제5항에 있어서, 상기 금속이 니켈인 방법.
  7. 제5항에 있어서, 상기 제1금속층에 이어, 얇은 제2금속 층(23)을 상기 양쪽 주표면 및 상기 통공의 상기벽에 제공된 상기 제1금속층위에 전기도금함으로써 형성하는 방법.
  8. 제7항에 있어서, 상기 제2금속이 구리를 포함하는 방법.
  9. 제8항에 있어서, 상기 제2금속층을 형성한 다음, 제3금속층을 적어도 상기 제1주표면상의 상기 제2금속층위에, 그리고 상기 통공을 통하여 선택적으로 전기도금함으로써 형성하는 방법.
  10. 제9항에 있어서, 상기 제3금속이 구리인 방법.
  11. 제9항에 있어서, 상기 제3금속의 선택적 전기도금에 앞서, 상기 제2금속을 습윤제에 노출시키는 방법.
  12. 제11항에 있어서, 상기 습윤제가 황산 라우릴 암모늄을 포함하는 방법.
  13. 제10항에 있어서, 상기 구리는 황산구리를 수용하는 18 내지 22℃ 범위의 온도로 유지시킨 조내에 상기 절연물질을 침수시키고 상기 조내에 가스를 주입하여 상기 조를 교반하므로써 전기도금되는 방법.
  14. 제13항에 있어서, 상기 가스는 400내지 750SCCM의 유량으로 주입하는 방법.
  15. 제1항에 있어서, 상기 두 어레이의 상기 접착패드들을 열압축 접착에 의해 접착되는 방법.
  16. 제1항에 있어서, 상기 제2접착패드 어레이는 상기 반도체 칩 표면의 외주부 근방의 1패드들과 상기 반도체 표면상의 상기 제1패드들의 안쪽에 위치한 제2패드들을 포함하는 방법.
  17. 제1항에 있어서, 상기 통공시 상기 직경은 100미크론 보다 작은 방법.
  18. 제1 및 제2주표면을 갖는 가요성 절연물질(11)과, 상기 제1주표면에 형성된 다수의 전도성 핑거(12)와, 상기 절연물질을 통하여 상기 제1주표면으로부터 상기 제2표면까지 연장되어 형성된 통공(30)의 어레이를 포함하는 장치에 있어서, 상기 제1주요면으로부터 연장되어 상기 통공을 통하고 상기 제2주표면에 있는 제1접착패드 어레이(20)내에서 끝나는 도금된 전도성 물질과, 상기 제1접착패드 어레이에 전기적 및 기계적으로 접착된 제2접착패드(40)어레이를 가지는 반도체 칩(41)을 특징으로 하는 장치.
  19. 제8항에 있어서, 상기 절연물질이 폴리이미드를 포함하는 장치.
  20. 제8항에 있어서, 상기 전동성 핑거 및 상기 도금된 전도성 물질이 구리를 포함하는 장치.
  21. 제20항에 있어서, 상기 전도성 핑거 및 상기 도금된 물질이 상기 제1주표면과 상기 통공의 벽에 얇은 무전해 도금층(22)을 더 포함하는 장치.
  22. 제1항에 있어서, 상기 제1접착패드 어레이가 상기 통공을 에워싸는 상기 제2주표면상에 형성된 랜드 영역을 포함하는 장치.
  23. 제18항에 있어서, 상기 제2접착패드 어레이가 상기 반도체 칩 표면의 외주부 상의 제1세트와 상기 제1세트 안쪽에 위치된 제2세트를 포함하는 장치.
  24. 제18항에 있어서, 상기 통공의 상기 직경이 100미크론 보다 작은 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930003127A 1992-03-04 1993-03-03 반도체 칩에 대한 전기적 접착 방법 및 그 장치 KR100288405B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/845,898 US5355019A (en) 1992-03-04 1992-03-04 Devices with tape automated bonding
US845,898 1992-03-04

Publications (2)

Publication Number Publication Date
KR930020618A true KR930020618A (ko) 1993-10-20
KR100288405B1 KR100288405B1 (ko) 2001-05-02

Family

ID=25296360

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930003127A KR100288405B1 (ko) 1992-03-04 1993-03-03 반도체 칩에 대한 전기적 접착 방법 및 그 장치

Country Status (5)

Country Link
US (1) US5355019A (ko)
EP (1) EP0559384A3 (ko)
JP (1) JP2823771B2 (ko)
KR (1) KR100288405B1 (ko)
TW (1) TW223182B (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995028005A2 (en) * 1994-04-07 1995-10-19 Vlsi Technology, Inc. Staggered pad array
JP3484554B2 (ja) * 1995-02-28 2004-01-06 日本テキサス・インスツルメンツ株式会社 半導体装置
JP3404446B2 (ja) * 1996-04-24 2003-05-06 シャープ株式会社 テープキャリアパッケージ及びそのテープキャリアパッケージを備えた液晶表示装置
GB2312988A (en) * 1996-05-10 1997-11-12 Memory Corp Plc Connecting a semiconductor die to a carrier
US5753976A (en) * 1996-06-14 1998-05-19 Minnesota Mining And Manufacturing Company Multi-layer circuit having a via matrix interlayer connection
JP3050807B2 (ja) * 1996-06-19 2000-06-12 イビデン株式会社 多層プリント配線板
JP3050812B2 (ja) 1996-08-05 2000-06-12 イビデン株式会社 多層プリント配線板
CN1059982C (zh) * 1997-08-28 2000-12-27 华通电脑股份有限公司 制造集成电路封装电路板的方法
JPH11238831A (ja) * 1997-12-16 1999-08-31 Shinko Electric Ind Co Ltd テープキャリア及びその製造方法
JP3846094B2 (ja) * 1998-03-17 2006-11-15 株式会社デンソー 半導体装置の製造方法
TW401632B (en) * 1998-03-26 2000-08-11 Fujitsu Ltd Resin molded semiconductor device and method of manufacturing semiconductor package
US7088002B2 (en) 2000-12-18 2006-08-08 Intel Corporation Interconnect
US7030472B2 (en) * 2004-04-01 2006-04-18 Agere Systems Inc. Integrated circuit device having flexible leadframe
US7262444B2 (en) * 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
US7829386B2 (en) * 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
JP4942629B2 (ja) * 2007-12-11 2012-05-30 三菱電機株式会社 電力用半導体モジュール

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2318592A (en) * 1940-02-24 1943-05-11 Du Pont Electrodeposition
US3269861A (en) * 1963-06-21 1966-08-30 Day Company Method for electroless copper plating
US3832769A (en) * 1971-05-26 1974-09-03 Minnesota Mining & Mfg Circuitry and method
US3791848A (en) * 1972-05-19 1974-02-12 Western Electric Co A method of improving the adherence of a metal deposit to a polyimide surface
US3868724A (en) * 1973-11-21 1975-02-25 Fairchild Camera Instr Co Multi-layer connecting structures for packaging semiconductor devices mounted on a flexible carrier
JPS5353766A (en) * 1976-10-26 1978-05-16 Suwa Seikosha Kk Tape carrier tape
JPS6046543B2 (ja) * 1978-09-11 1985-10-16 富士通株式会社 樹脂フイルムのスル−ホ−ル形成法
US4435740A (en) * 1981-10-30 1984-03-06 International Business Machines Corporation Electric circuit packaging member
JPS61111561A (ja) * 1984-10-05 1986-05-29 Fujitsu Ltd 半導体装置
GB8500906D0 (en) * 1985-01-15 1985-02-20 Prestwick Circuits Ltd Printed circuit boards
US4814855A (en) * 1986-04-29 1989-03-21 International Business Machines Corporation Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape
EP0293838A3 (en) * 1987-06-02 1989-09-06 Kabushiki Kaisha Toshiba Ic package for high-speed semiconductor integrated circuit device
US5089881A (en) * 1988-11-03 1992-02-18 Micro Substrates, Inc. Fine-pitch chip carrier
SG49842A1 (en) * 1988-11-09 1998-06-15 Nitto Denko Corp Wiring substrate film carrier semiconductor device made by using the film carrier and mounting structure comprising the semiconductor
JPH02215145A (ja) * 1989-02-16 1990-08-28 Furukawa Electric Co Ltd:The テープキャリアの製造方法
US5065228A (en) * 1989-04-04 1991-11-12 Olin Corporation G-TAB having particular through hole
US4976808A (en) * 1989-04-22 1990-12-11 Sumitomo Metal Mining Company Limited Process for removing a polyimide resin by dissolution
JPH03120735A (ja) * 1989-10-04 1991-05-22 Sumitomo Metal Mining Co Ltd 二層フィルムキャリアの製造方法
JP2753746B2 (ja) * 1989-11-06 1998-05-20 日本メクトロン株式会社 Ｉｃ搭載用可撓性回路基板及びその製造法
US5065227A (en) * 1990-06-04 1991-11-12 International Business Machines Corporation Integrated circuit packaging using flexible substrate
US5313367A (en) * 1990-06-26 1994-05-17 Seiko Epson Corporation Semiconductor device having a multilayer interconnection structure
DE69118308T2 (de) * 1990-10-24 1996-08-08 Nec Corp Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung

Also Published As

Publication number Publication date
EP0559384A2 (en) 1993-09-08
TW223182B (ko) 1994-05-01
US5355019A (en) 1994-10-11
JP2823771B2 (ja) 1998-11-11
JPH0621142A (ja) 1994-01-28
EP0559384A3 (en) 1993-10-20
KR100288405B1 (ko) 2001-05-02

Similar Documents

Publication Publication Date Title
KR930020618A (ko) 반도체 칩에 대한 전기적 접착 방법 및 반도체 장치
KR960006763B1 (ko) 배선기판과 그 제조방법, 박막 캐리어, 반도체 장치 및 그 장착구조와 반도체 장치장착 방법
JP3807508B2 (ja) 誘電層を備えた超小形電子リード構造体
JP2000188358A (ja) 半導体装置
KR20070113112A (ko) 배선 기판, 그 제조 방법 및 반도체 장치
EP0729181A2 (en) Resin sealing type semiconductor device and method of making the same
JPS6170743A (ja) 電気相互連結テ−プ
JPS61160946A (ja) 半導体装置の接続構造体
JPS5571052A (en) Substrate for semiconductor device
JPH06347480A (ja) プローブ構造
KR100721725B1 (ko) 분리 가능한 리드를 구비한 소자
KR100359174B1 (ko) 필름캐리어및이필름캐리어를이용한반도체장치
JP2782870B2 (ja) リードフレーム
JPS5688330A (en) Fixing method for lead wire
JPS56161664A (en) Manufacture of lead for connecting semiconductor device
JP3324471B2 (ja) 両面配線ｔａｂ用テープ
JPS56142659A (en) Semiconductor device
JPH02129938A (ja) 配線基板およびその製法
JP2000200848A (ja) 電子部品実装用回路基板及び半導体装置
JPS62122278A (ja) 高周波高出力ｆｅｔの製造方法
JPH0922956A (ja) 半導体装置
JPS6153755A (ja) 半導体装置
JP2000260829A (ja) 半導体装置用テープキャリア及びその製造方法
JPS6417450A (en) Formation of bump
JPH04137542A (ja) テープキャリア

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130117

Year of fee payment: 13

EXPY Expiration of term