JPS5688330A - Fixing method for lead wire - Google Patents
Fixing method for lead wireInfo
- Publication number
- JPS5688330A JPS5688330A JP16617379A JP16617379A JPS5688330A JP S5688330 A JPS5688330 A JP S5688330A JP 16617379 A JP16617379 A JP 16617379A JP 16617379 A JP16617379 A JP 16617379A JP S5688330 A JPS5688330 A JP S5688330A
- Authority
- JP
- Japan
- Prior art keywords
- silver
- lead wire
- roughness
- layer
- nail head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To automate the nail head bonding of gold wire by providing a silver plated layer having specified roughness of the surface on a metal conducting wire on an insulating substrate. CONSTITUTION:A copper foil 3 is bonded to the insulating layer 2 of the substrate 10 having the thin insulating layer 2 on Al 1, and a silver plated layer 4 is selectively formed. The copper foil 3 is etched out with the silver layer 4 as a mask, and the conducting path is formed. In this case, if the roughness of the surface of the silver plating 4 is about 1.5-5mu, the anchor effect is yielded when the lead wire 6 is fixed, the fixed cross sectional area is increased, and the lead wire can be fixed to the uncontaminated surface whose tip of the convex portion is not deformed. Therefore, the excellent nail head bonding is realized only by the selection of the roughness of the surface of the silver plated layer, and the automation by the nail head bonding without directivity becomes possible.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16617379A JPS5688330A (en) | 1979-12-19 | 1979-12-19 | Fixing method for lead wire |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16617379A JPS5688330A (en) | 1979-12-19 | 1979-12-19 | Fixing method for lead wire |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5688330A true JPS5688330A (en) | 1981-07-17 |
Family
ID=15826419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16617379A Pending JPS5688330A (en) | 1979-12-19 | 1979-12-19 | Fixing method for lead wire |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5688330A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0964446A3 (en) * | 1998-06-04 | 2001-02-07 | Ford Motor Company | An electronic circuit assembly |
JP2015220429A (en) * | 2014-05-21 | 2015-12-07 | ローム株式会社 | Semiconductor device |
EP3246958A1 (en) * | 2016-05-17 | 2017-11-22 | Point Engineering Co., Ltd. | Method for manufacturing chip-mounting substrate, and chip-mounting substrate |
CN110731129A (en) * | 2017-06-09 | 2020-01-24 | 电化株式会社 | Ceramic circuit board |
-
1979
- 1979-12-19 JP JP16617379A patent/JPS5688330A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0964446A3 (en) * | 1998-06-04 | 2001-02-07 | Ford Motor Company | An electronic circuit assembly |
JP2015220429A (en) * | 2014-05-21 | 2015-12-07 | ローム株式会社 | Semiconductor device |
EP3246958A1 (en) * | 2016-05-17 | 2017-11-22 | Point Engineering Co., Ltd. | Method for manufacturing chip-mounting substrate, and chip-mounting substrate |
US10868221B2 (en) | 2016-05-17 | 2020-12-15 | Point Engineering Co., Ltd. | Method for manufacturing chip-mounting substrate, and chip-mounting substrate |
CN110731129A (en) * | 2017-06-09 | 2020-01-24 | 电化株式会社 | Ceramic circuit board |
CN110731129B (en) * | 2017-06-09 | 2024-01-09 | 电化株式会社 | Ceramic circuit board |
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